/*
* MPC85xx Internal Memory Map
*
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
*
* Copyright(c) 2002,2003 Motorola Inc.
* Xianghua Xiao (x.xiao@motorola.com)
#include <asm/types.h>
#include <asm/fsl_dma.h>
#include <asm/fsl_i2c.h>
+#include <asm/fsl_ifc.h>
#include <asm/fsl_lbc.h>
#include <asm/fsl_fman.h>
u32 capture_ext_address; /* Error Extended Addr Capture */
u32 err_sbe; /* Single-Bit ECC Error Management */
u8 res11[164];
- u32 debug_1;
- u32 debug_2;
- u32 debug_3;
- u32 debug_4;
- u32 debug_5;
- u32 debug_6;
- u32 debug_7;
- u32 debug_8;
- u32 debug_9;
- u32 debug_10;
- u32 debug_11;
- u32 debug_12;
- u32 debug_13;
- u32 debug_14;
- u32 debug_15;
- u32 debug_16;
- u32 debug_17;
- u32 debug_18;
- u8 res12[184];
+ u32 debug[32]; /* debug_1 to debug_32 */
+ u8 res12[128];
} ccsr_ddr_t;
#define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
u32 cpcerreaddr; /* error extended address */
u32 cpcerraddr; /* error address */
u32 cpcerrctl; /* error control */
- u32 res9[105]; /* pad out to 4k */
+ u32 res9[41]; /* pad out to 4k */
+ u32 cpchdbcr0; /* hardware debug control register 0 */
+ u32 res10[63]; /* pad out to 4k */
} cpc_corenet_t;
#define CPC_CSR0_CE 0x80000000 /* Cache Enable */
#define CPC_SRCR0_SRAMSZ_32_WAY 0x0000000a
#define CPC_SRCR0_SRAMEN 0x00000001
#define CPC_ERRDIS_TMHITDIS 0x00000080 /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS 0x08000000
+#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS 0x01000000
+#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS 0x00400000
#endif /* CONFIG_SYS_FSL_CPC */
/* Global Utilities Block */
#define MPC85xx_PORBMSR_HA_SHIFT 16
u32 porimpscr; /* POR I/O impedance status & control */
u32 pordevsr; /* POR I/O device status regsiter */
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
+#else
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#endif
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
+#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
+#else
+#if defined(CONFIG_P1010)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
#define MPC85xx_PORDEVSR_IO_SEL 0x00780000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19
+#endif /* if defined(CONFIG_P1010) */
#endif
#define MPC85xx_PORDEVSR_PCI2_ARB 0x00040000
#define MPC85xx_PORDEVSR_PCI1_ARB 0x00020000
#define MPC85xx_PMUXCR_SD_DATA 0x80000000
#define MPC85xx_PMUXCR_SDHC_CD 0x40000000
#define MPC85xx_PMUXCR_SDHC_WP 0x20000000
+#define MPC85xx_PMUXCR_TDM_ENA 0x00800000
+#define MPC85xx_PMUXCR_QE0 0x00008000
+#define MPC85xx_PMUXCR_QE1 0x00004000
+#define MPC85xx_PMUXCR_QE2 0x00002000
+#define MPC85xx_PMUXCR_QE3 0x00001000
+#define MPC85xx_PMUXCR_QE4 0x00000800
+#define MPC85xx_PMUXCR_QE5 0x00000400
+#define MPC85xx_PMUXCR_QE6 0x00000200
+#define MPC85xx_PMUXCR_QE7 0x00000100
+#define MPC85xx_PMUXCR_QE8 0x00000080
+#define MPC85xx_PMUXCR_QE9 0x00000040
+#define MPC85xx_PMUXCR_QE10 0x00000020
+#define MPC85xx_PMUXCR_QE11 0x00000010
+#define MPC85xx_PMUXCR_QE12 0x00000008
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK 0x0001cc00
+#define MPC85xx_PMUXCR_TDM 0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK 0x00600000
+#define MPC85xx_PMUXCR_SPI 0x00000000
+#endif
u32 pmuxcr2; /* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK 0x001f1000
+#define MPC85xx_PMUXCR2_USB 0x00150000
+#endif
u8 res6[8];
u32 devdisr; /* Device disable control */
#define MPC85xx_DEVDISR_PCI1 0x80000000
u8 res9[12];
u32 pvr; /* Processor version */
u32 svr; /* System version */
- u8 res10a[8];
+ u8 res10[8];
u32 rstcr; /* Reset control */
#if defined(CONFIG_MPC8568)||defined(CONFIG_MPC8569)
- u8 res10b[76];
+ u8 res11a[76];
par_io_t qe_par_io[7];
- u8 res10c[1600];
+ u8 res11b[1600];
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
+ defined(CONFIG_P1021) || defined(CONFIG_P1025)
+ u8 res11a[12];
+ u32 iovselsr;
+ u8 res11b[60];
+ par_io_t qe_par_io[3];
+ u8 res11c[1496];
#else
- u8 res10b[1868];
+ u8 res11a[1868];
#endif
u32 clkdvdr; /* Clock Divide register */
- u8 res10d[1532];
+ u8 res12[1532];
u32 clkocr; /* Clock out select */
- u8 res11[12];
+ u8 res13[12];
u32 ddrdllcr; /* DDR DLL control */
- u8 res12[12];
+ u8 res14[12];
u32 lbcdllcr; /* LBC DLL control */
- u8 res13[248];
+ u8 res15[248];
u32 lbiuiplldcr0; /* LBIU PLL Debug Reg 0 */
u32 lbiuiplldcr1; /* LBIU PLL Debug Reg 1 */
u32 ddrioovcr; /* DDR IO Override Control */
u32 tsec12ioovcr; /* eTSEC 1/2 IO override control */
u32 tsec34ioovcr; /* eTSEC 3/4 IO override control */
- u8 res15[61648];
+ u8 res16[52];
+ u32 sdhcdcr; /* SDHC debug control register */
+ u8 res17[61592];
} ccsr_gur_t;
#endif
+#define SDHCDCR_CD_INV 0x80000000 /* invert SDHC card detect */
+
typedef struct serdes_corenet {
struct {
u32 rstctl; /* Reset Control Register */
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000
#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000
#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000
-#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET 0x318000
-#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET 0x31a000
+#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000
#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000
#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000
#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000
#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000
#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000
#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000
#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000
#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000
#define CONFIG_SYS_MPC85xx_USB_OFFSET 0x22000
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
#define CONFIG_SYS_FSL_CPC_ADDR \
(CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
#define CONFIG_SYS_FSL_CORENET_PME_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
#define CONFIG_SYS_MPC85xx_GUTS_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
#define CONFIG_SYS_LBC_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_IFC_ADDR \
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
#define CONFIG_SYS_MPC85xx_ESPI_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
#define CONFIG_SYS_MPC85xx_PCIX_ADDR \
#define CONFIG_SYS_MPC85xx_CPM_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
- (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+ (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
(CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \
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