Merge branch 'master' of git://git.denx.de/u-boot-x86

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 7beb6a7bc5c2c1fb4fdc8765efaabbb7f3eaf82d..b51017b5509815521e2eec14e3c486e8d85d33d9 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1923,6 +1923,7 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_SD_DATA         0x80000000
 #define MPC85xx_PMUXCR_SDHC_CD         0x40000000
 #define MPC85xx_PMUXCR_SDHC_WP         0x20000000
+#define MPC85xx_PMUXCR_TDM_ENA         0x00800000
 #define MPC85xx_PMUXCR_QE0             0x00008000
 #define MPC85xx_PMUXCR_QE1             0x00004000
 #define MPC85xx_PMUXCR_QE2             0x00002000
@@ -1936,7 +1937,17 @@ typedef struct ccsr_gur {
 #define MPC85xx_PMUXCR_QE10            0x00000020
 #define MPC85xx_PMUXCR_QE11            0x00000010
 #define MPC85xx_PMUXCR_QE12            0x00000008
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR_TDM_MASK                0x0001cc00
+#define MPC85xx_PMUXCR_TDM             0x00014800
+#define MPC85xx_PMUXCR_SPI_MASK                0x00600000
+#define MPC85xx_PMUXCR_SPI             0x00000000
+#endif
        u32     pmuxcr2;        /* Alt. function signal multiplex control 2 */
+#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
+#define MPC85xx_PMUXCR2_ETSECUSB_MASK  0x001f1000
+#define MPC85xx_PMUXCR2_USB            0x00150000
+#endif
        u8      res6[8];
        u32     devdisr;        /* Device disable control */
 #define MPC85xx_DEVDISR_PCI1           0x80000000
@@ -1998,10 +2009,14 @@ typedef struct ccsr_gur {
        u32     ddrioovcr;      /* DDR IO Override Control */
        u32     tsec12ioovcr;   /* eTSEC 1/2 IO override control */
        u32     tsec34ioovcr;   /* eTSEC 3/4 IO override control */
-       u8      res16[61648];
+       u8      res16[52];
+       u32     sdhcdcr;        /* SDHC debug control register */
+       u8      res17[61592];
 } ccsr_gur_t;
 #endif
 
+#define SDHCDCR_CD_INV         0x80000000 /* invert SDHC card detect */
+
 typedef struct serdes_corenet {
        struct {
                u32     rstctl; /* Reset Control Register */