]> git.sur5r.net Git - u-boot/blobdiff - arch/powerpc/include/asm/immap_85xx.h
powerpc/fsl-corenet: remove dead variant symbols
[u-boot] / arch / powerpc / include / asm / immap_85xx.h
index 53d563ed0a030bde68db52a686583bcc43ae2a71..c2d33b1d20bbaeabb75df9e5818770d6b94c9ca5 100644 (file)
@@ -1729,6 +1729,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_DEVDISR2_DTSEC2_2  0x00004000
 #define FSL_CORENET_DEVDISR2_DTSEC2_3  0x00002000
 #define FSL_CORENET_DEVDISR2_DTSEC2_4  0x00001000
+#define FSL_CORENET_DEVDISR2_DTSEC2_5  0x00000800
 #define FSL_CORENET_NUM_DEVDISR                2
        u8      res7[8];
        u32     powmgtcsr;      /* Power management status & control */
@@ -1758,13 +1759,14 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR5_DDR_SYNC            0x00000080
 #define FSL_CORENET_RCWSR5_DDR_SYNC_SHIFT               7
 #define FSL_CORENET_RCWSR5_SRDS_EN             0x00002000
+#define FSL_CORENET_RCWSR6_BOOT_LOC    0x0f800000
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B2         0x3c000000 /* bits 162..165 */
 #define FSL_CORENET_RCWSRn_SRDS_LPD_B3         0x003c0000 /* bits 170..173 */
 #define FSL_CORENET_RCWSR7_MCK_TO_PLAT_RAT     0x00400000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B1         0x00e00000
 #define FSL_CORENET_RCWSR8_HOST_AGT_B2         0x00100000
 #define FSL_CORENET_RCWSR11_EC1                        0x00c00000 /* bits 360..361 */
-#if defined(CONFIG_PPC_P4080) || defined(CONFIG_PPC_P3060)
+#ifdef CONFIG_PPC_P4080
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC1             0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_USB1               0x00800000
 #define FSL_CORENET_RCWSR11_EC2                        0x001c0000 /* bits 363..365 */
@@ -1772,7 +1774,7 @@ typedef struct ccsr_gur {
 #define FSL_CORENET_RCWSR11_EC2_FM1_DTSEC2             0x00080000
 #define FSL_CORENET_RCWSR11_EC2_USB2                   0x00100000
 #endif
-#if defined(CONFIG_PPC_P2040) || defined(CONFIG_PPC_P2041) \
+#if defined(CONFIG_PPC_P2041) \
        || defined(CONFIG_PPC_P3041) || defined(CONFIG_PPC_P5020)
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII       0x00000000
 #define FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII         0x00800000
@@ -2259,8 +2261,7 @@ typedef struct ccsr_gur {
        u8      res11a[76];
        par_io_t qe_par_io[7];
        u8      res11b[1600];
-#elif defined(CONFIG_P1012) || defined(CONFIG_P1016) || \
-      defined(CONFIG_P1021) || defined(CONFIG_P1025)
+#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
        u8      res11a[12];
        u32     iovselsr;
        u8      res11b[60];