powerpc/85xx: Refactor Qman/Portal support to be shared between SoCs

[u-boot] / arch / powerpc / include / asm / immap_85xx.h

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index a5e56d8074f718ce7a198e917d149e5239ee369f..d26d648b139db880c7baad0f46a917d4737c3aa6 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1,7 +1,7 @@
 /*
  * MPC85xx Internal Memory Map
  *
- * Copyright 2007-2010 Freescale Semiconductor, Inc.
+ * Copyright 2007-2011 Freescale Semiconductor, Inc.
  *
  * Copyright(c) 2002,2003 Motorola Inc.
  * Xianghua Xiao (x.xiao@motorola.com)
@@ -31,7 +31,9 @@
 #include <asm/types.h>
 #include <asm/fsl_dma.h>
 #include <asm/fsl_i2c.h>
+#include <asm/fsl_ifc.h>
 #include <asm/fsl_lbc.h>
+#include <asm/fsl_fman.h>
 
 typedef struct ccsr_local {
        u32     ccsrbarh;       /* CCSR Base Addr High */
@@ -221,25 +223,8 @@ typedef struct ccsr_ddr {
        u32     capture_ext_address;    /* Error Extended Addr Capture */
        u32     err_sbe;                /* Single-Bit ECC Error Management */
        u8      res11[164];
-       u32     debug_1;
-       u32     debug_2;
-       u32     debug_3;
-       u32     debug_4;
-       u32     debug_5;
-       u32     debug_6;
-       u32     debug_7;
-       u32     debug_8;
-       u32     debug_9;
-       u32     debug_10;
-       u32     debug_11;
-       u32     debug_12;
-       u32     debug_13;
-       u32     debug_14;
-       u32     debug_15;
-       u32     debug_16;
-       u32     debug_17;
-       u32     debug_18;
-       u8      res12[184];
+       u32     debug[32];              /* debug_1 to debug_32 */
+       u8      res12[128];
 } ccsr_ddr_t;
 
 #define DDR_EOR_RD_BDW_OPT_DIS 0x80000000 /* Read BDW Opt. disable */
@@ -1588,7 +1573,9 @@ typedef struct cpc_corenet {
        u32     cpcerreaddr;    /* error extended address */
        u32     cpcerraddr;     /* error address */
        u32     cpcerrctl;      /* error control */
-       u32     res9[105];      /* pad out to 4k */
+       u32     res9[41];       /* pad out to 4k */
+       u32     cpchdbcr0;      /* hardware debug control register 0 */
+       u32     res10[63];      /* pad out to 4k */
 } cpc_corenet_t;
 
 #define CPC_CSR0_CE    0x80000000      /* Cache Enable */
@@ -1615,6 +1602,9 @@ typedef struct cpc_corenet {
 #define CPC_SRCR0_SRAMSZ_32_WAY        0x0000000a
 #define CPC_SRCR0_SRAMEN       0x00000001
 #define        CPC_ERRDIS_TMHITDIS     0x00000080      /* multi-way hit disable */
+#define CPC_HDBCR0_CDQ_SPEC_DIS        0x08000000
+#define CPC_HDBCR0_TAG_ECC_SCRUB_DIS   0x01000000
+#define CPC_HDBCR0_DATA_ECC_SCRUB_DIS  0x00400000
 #endif /* CONFIG_SYS_FSL_CPC */
 
 /* Global Utilities Block */
@@ -1875,8 +1865,13 @@ typedef struct ccsr_gur {
 #define MPC85xx_PORBMSR_HA_SHIFT       16
        u32     porimpscr;      /* POR I/O impedance status & control */
        u32     pordevsr;       /* POR I/O device status regsiter */
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS    0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS    0x08000000
+#else
 #define MPC85xx_PORDEVSR_SGMII1_DIS    0x20000000
 #define MPC85xx_PORDEVSR_SGMII2_DIS    0x10000000
+#endif
 #define MPC85xx_PORDEVSR_SGMII3_DIS    0x08000000
 #define MPC85xx_PORDEVSR_SGMII4_DIS    0x04000000
 #define MPC85xx_PORDEVSR_SRDS2_IO_SEL  0x38000000
@@ -1884,9 +1879,17 @@ typedef struct ccsr_gur {
 #if defined(CONFIG_P1013) || defined(CONFIG_P1022)
 #define MPC85xx_PORDEVSR_IO_SEL                0x007c0000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  18
+#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL                0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
+#else
+#if defined(CONFIG_P1010)
+#define MPC85xx_PORDEVSR_IO_SEL                0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT  21
 #else
 #define MPC85xx_PORDEVSR_IO_SEL                0x00780000
 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT  19
+#endif /* if defined(CONFIG_P1010) */
 #endif
 #define MPC85xx_PORDEVSR_PCI2_ARB      0x00040000
 #define MPC85xx_PORDEVSR_PCI1_ARB      0x00020000
@@ -2062,7 +2065,7 @@ typedef struct ccsr_sec {
        struct {
                u32     ms;     /* Job Ring LIODN Register, MS */
                u32     ls;     /* Job Ring LIODN Register, LS */
-       } jqliodnr[4];
+       } jrliodnr[4];
        u8      res2[0x30];
        struct {
                u32     ms;     /* RTIC LIODN Register, MS */
@@ -2107,8 +2110,8 @@ typedef struct ccsr_sec {
 #define SEC_CTPR_MS_AXI_LIODN          0x08000000
 #define SEC_CTPR_MS_QI                 0x02000000
 #define SEC_RVID_MA                    0x0f000000
-#define SEC_CHANUM_MS_JQNUM_MASK       0xf0000000
-#define SEC_CHANUM_MS_JQNUM_SHIFT      28
+#define SEC_CHANUM_MS_JRNUM_MASK       0xf0000000
+#define SEC_CHANUM_MS_JRNUM_SHIFT      28
 #define SEC_CHANUM_MS_DECONUM_MASK     0x0f000000
 #define SEC_CHANUM_MS_DECONUM_SHIFT    24
 #endif
@@ -2201,8 +2204,8 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x221000
 #define CONFIG_SYS_FSL_SEC_OFFSET              0x300000
 #define CONFIG_SYS_FSL_CORENET_PME_OFFSET      0x316000
-#define CONFIG_SYS_FSL_CORENET_QMAN_OFFSET     0x318000
-#define CONFIG_SYS_FSL_CORENET_BMAN_OFFSET     0x31a000
+#define CONFIG_SYS_FSL_QMAN_OFFSET             0x318000
+#define CONFIG_SYS_FSL_BMAN_OFFSET             0x31a000
 #define CONFIG_SYS_FSL_FM1_OFFSET              0x400000
 #define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET       0x488000
 #define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET       0x489000
@@ -2238,6 +2241,7 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_GPIO_OFFSET         0xF000
 #define CONFIG_SYS_MPC85xx_SATA1_OFFSET                0x18000
 #define CONFIG_SYS_MPC85xx_SATA2_OFFSET                0x19000
+#define CONFIG_SYS_MPC85xx_IFC_OFFSET          0x1e000
 #define CONFIG_SYS_MPC85xx_L2_OFFSET           0x20000
 #define CONFIG_SYS_MPC85xx_DMA_OFFSET          0x21000
 #define CONFIG_SYS_MPC85xx_USB_OFFSET          0x22000
@@ -2251,6 +2255,12 @@ typedef struct ccsr_pme {
 #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET      0xE3100
 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET      0xE3000
 #define CONFIG_SYS_MPC85xx_CPM_OFFSET          0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET             0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET             0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET              0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET       0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET       0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET       0x1e0000
 #endif
 
 #define CONFIG_SYS_MPC85xx_PIC_OFFSET          0x40000
@@ -2258,10 +2268,10 @@ typedef struct ccsr_pme {
 
 #define CONFIG_SYS_FSL_CPC_ADDR        \
        (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_QMAN_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_QMAN_OFFSET)
-#define CONFIG_SYS_FSL_CORENET_BMAN_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_BMAN_OFFSET)
+#define CONFIG_SYS_FSL_QMAN_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET)
+#define CONFIG_SYS_FSL_BMAN_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_PME_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET)
 #define CONFIG_SYS_MPC85xx_GUTS_ADDR \
@@ -2280,6 +2290,8 @@ typedef struct ccsr_pme {
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
+#define CONFIG_SYS_IFC_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
 #define CONFIG_SYS_MPC85xx_PCIX_ADDR \
@@ -2298,12 +2310,12 @@ typedef struct ccsr_pme {
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC85xx_ESDHC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET)
-#define CONFIG_SYS_MPC85xx_PIC_ADDR \
+#define CONFIG_SYS_MPC8xxx_PIC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET)
 #define CONFIG_SYS_MPC85xx_CPM_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_CPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES1_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET)
 #define CONFIG_SYS_MPC85xx_SERDES2_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET)
 #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \