powerpc/mp: add support for discontiguous cores

[u-boot] / arch / powerpc / include / asm / ppc440sp.h

diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h
index d4e62b6c1ade8a3892e88ad454e534a7fe9d7f8c..cc2ff681230ae4143e71a10364fd7c183972faf0 100644 (file)
--- a/arch/powerpc/include/asm/ppc440sp.h
+++ b/arch/powerpc/include/asm/ppc440sp.h
@@ -23,13 +23,19 @@
 
 #define CONFIG_SDRAM_PPC4xx_IBM_DDR2   /* IBM DDR(2) controller */
 
-#define CONFIG_SYS_PPC4xx_PLB4_ARBITER
-
 /*
  * Some SoC specific registers (not common for all 440 SoC's)
  */
-#define GPIO0_BASE     (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
 
+/* Memory mapped register */
+#define CONFIG_SYS_PERIPHERAL_BASE     0xf0000000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_PERIPHERAL_BASE + 0x0200)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+
+#define GPIO0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0700)
+
+/* SDR's */
 #define SDR0_PCI0      0x0300
 #define SDR0_SDSTP2    0x0022
 #define SDR0_SDSTP3    0x0023
@@ -61,7 +67,7 @@
 #define PLLD_LFBDV_MASK                0x0000003f  /* PLL Local Feedback Divisor */
 
 #define OPBDDV_MASK            0x03000000  /* OPB Clock Divisor Register */
-#define PERDV_MASK             0x07000000  /* Periferal Clock Divisor */
+#define PERDV_MASK             0x07000000  /* Peripheral Clock Divisor */
 #define PRADV_MASK             0x07000000  /* Primary Divisor A */
 #define PRBDV_MASK             0x07000000  /* Primary Divisor B */
 #define SPCID_MASK             0x03000000  /* Sync PCI Divisor  */
@@ -71,7 +77,7 @@
 #define PLLSYS1_PERCLK_DIV_MASK 0x03000000     /* Peripheral Clk Divisor */
 #define PLLSYS1_MAL_DIV_MASK   0x00c00000      /* MAL Clk Divisor */
 #define PLLSYS1_RW_MASK                0x00300000      /* ROM width */
-#define PLLSYS1_EAR_MASK       0x00080000      /* ERAP Addres reset vector */
+#define PLLSYS1_EAR_MASK       0x00080000      /* ERAP Address reset vector */
 #define PLLSYS1_PAE_MASK       0x00040000      /* PCI arbitor enable */
 #define PLLSYS1_PCHE_MASK      0x00020000      /* PCI host config enable */
 #define PLLSYS1_PISE_MASK      0x00010000      /* PCI init seq. enable */