#define CONFIG_NAND_NDFC
-#define CONFIG_SYS_PPC4xx_PLB4_ARBITER
-
/*
* Some SoC specific registers
*/
-#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00)
-#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00)
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */
+
+#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
+#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
+
+#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
+#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
/* DCR */
#define AHB_TOP 0x00a4