Merge git://git.denx.de/u-boot-sunxi

[u-boot] / arch / powerpc / include / asm / ppc460ex_gt.h

diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h
index a535f7563720c2bc779d9a1ec7164ab7b40be289..ea019aafdb03fdc00576f95d1e134cb5dfe80af5 100644 (file)
--- a/arch/powerpc/include/asm/ppc460ex_gt.h
+++ b/arch/powerpc/include/asm/ppc460ex_gt.h
@@ -2,20 +2,7 @@
  * (C) Copyright 2010
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _PPC460EX_GT_H_
@@ -25,14 +12,22 @@
 
 #define CONFIG_NAND_NDFC
 
-#define CONFIG_SYS_PPC4xx_PLB4_ARBITER
-
 /*
  * Some SoC specific registers
  */
 
-#define GPIO0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x00000B00)
-#define GPIO1_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x00000C00)
+/* Memory mapped registers */
+#define CONFIG_SYS_PERIPHERAL_BASE     0xef600000 /* Internal Peripherals */
+
+#ifndef CONFIG_DM_SERIAL
+#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_PERIPHERAL_BASE + 0x0300)
+#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_PERIPHERAL_BASE + 0x0400)
+#define CONFIG_SYS_NS16550_COM3        (CONFIG_SYS_PERIPHERAL_BASE + 0x0500)
+#define CONFIG_SYS_NS16550_COM4        (CONFIG_SYS_PERIPHERAL_BASE + 0x0600)
+#endif
+
+#define GPIO0_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00)
+#define GPIO1_BASE             (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00)
 
 /* DCR */
 #define AHB_TOP                        0x00a4