Merge branch 'master' of git://www.denx.de/git/u-boot-socfpga

[u-boot] / arch / powerpc / include / asm / processor.h

diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index bcf6cfb097832fb0248d399fba4ad5697c4dcbb5..fdfca9086fb21320f1c164eae4ec9c6809786dcd 100644 (file)
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -7,8 +7,6 @@
  */
 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
 
-#include <linux/config.h>
-
 #include <asm/ptrace.h>
 #include <asm/types.h>
 
@@ -380,11 +378,16 @@
 #else
 #define SPRN_TCR       0x154   /* Book E Timer Control Register */
 #endif /* CONFIG_BOOKE */
+#ifdef CONFIG_E500MC
+#define  TCR_WP(x)             (((64-x)&0x3)<<30)| \
+                               (((64-x)&0x3c)<<15) /* WDT Period 2^x clocks*/
+#else
 #define   TCR_WP(x)            (((x)&0x3)<<30) /* WDT Period */
 #define     WP_2_17            0               /* 2^17 clocks */
 #define     WP_2_21            1               /* 2^21 clocks */
 #define     WP_2_25            2               /* 2^25 clocks */
 #define     WP_2_29            3               /* 2^29 clocks */
+#endif /* CONFIG_E500 */
 #define   TCR_WRC(x)           (((x)&0x3)<<28) /* WDT Reset Control */
 #define     WRC_NONE           0               /* No reset will occur */
 #define     WRC_CORE           1               /* Core reset will occur */
@@ -894,9 +897,6 @@
 #define PVR_405GP_RC   0x40110082
 #define PVR_405GP_RD   0x401100C4
 #define PVR_405GP_RE   0x40110145  /* same as pc405cr rev c */
-#define PVR_405CR_RA   0x40110041
-#define PVR_405CR_RB   0x401100C5
-#define PVR_405CR_RC   0x40110145  /* same as pc405gp rev e */
 #define PVR_405EP_RA   0x51210950
 #define PVR_405GPR_RB  0x50910951
 #define PVR_405EZ_RA   0x41511460
@@ -1116,12 +1116,13 @@
 #define SVR_T4240      0x824000
 #define SVR_T4120      0x824001
 #define SVR_T4160      0x824100
+#define SVR_T4080      0x824102
 #define SVR_C291       0x850000
 #define SVR_C292       0x850020
 #define SVR_C293       0x850030
 #define SVR_B4860      0X868000
 #define SVR_G4860      0x868001
-#define SVR_G4060      0x868003
+#define SVR_B4460      0x868003
 #define SVR_B4440      0x868100
 #define SVR_G4440      0x868101
 #define SVR_B4420      0x868102
@@ -1132,6 +1133,12 @@
 #define SVR_T1020      0x852100
 #define SVR_T1021      0x852101
 #define SVR_T1022      0x852102
+#define SVR_T1024      0x854000
+#define SVR_T1023      0x854100
+#define SVR_T1014      0x854400
+#define SVR_T1013      0x854500
+#define SVR_T2080      0x853000
+#define SVR_T2081      0x853100
 
 #define SVR_8610       0x80A000
 #define SVR_8641       0x809000
@@ -1195,12 +1202,17 @@ struct cpu_type {
        u32 soc_ver;
        u32 num_cores;
        u32 mask;       /* which cpu(s) actually exist */
+#ifdef CONFIG_HETROGENOUS_CLUSTERS
+       u32 dsp_num_cores;
+       u32 dsp_mask;   /* which DSP cpu(s) actually exist */
+#endif
 };
 
 struct cpu_type *identify_cpu(u32 ver);
 int fixup_cpu(void);
 
 int fsl_qoriq_core_to_cluster(unsigned int core);
+int fsl_qoriq_dsp_core_to_cluster(unsigned int core);
 
 #if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx)
 #define CPU_TYPE_ENTRY(n, v, nc) \
@@ -1347,26 +1359,12 @@ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 #if defined(CONFIG_8xx)
 #define _machine _MACH_8xx
 #define have_of 0
-#elif defined(CONFIG_OAK)
-#define _machine _MACH_oak
-#define have_of        0
 #elif defined(CONFIG_WALNUT)
 #define _machine _MACH_walnut
 #define have_of 0
-#elif defined(CONFIG_APUS)
-#define _machine _MACH_apus
-#define have_of 0
-#elif defined(CONFIG_GEMINI)
-#define _machine _MACH_gemini
-#define have_of 0
-#elif defined(CONFIG_8260)
+#elif defined(CONFIG_MPC8260)
 #define _machine _MACH_8260
 #define have_of 0
-#elif defined(CONFIG_SANDPOINT)
-#define _machine _MACH_sandpoint
-#elif defined(CONFIG_HIDDEN_DRAGON)
-#define _machine _MACH_hidden_dragon
-#define have_of 0
 #else
 #error "Machine not defined correctly"
 #endif