SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / sh / cpu / sh4 / cache.c

diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c
index dc75e3981cf55fdf7d2e4fee732f51b3d3fc9caa..50490904249330a1f2f779aeac4cb4040db5a4f3 100644 (file)
--- a/arch/sh/cpu/sh4/cache.c
+++ b/arch/sh/cpu/sh4/cache.c
@@ -1,66 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
- * (C) Copyright 2007
- * Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * (C) Copyright 2016 Vladimir Zapolskiy <vz@mleia.com>
+ * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  */
 
 #include <common.h>
 #include <command.h>
-#include <asm/processor.h>
 #include <asm/io.h>
-
-/*
- * Jump to P2 area.
- * When handling TLB or caches, we need to do it from P2 area.
- */
-#define jump_to_P2()                   \
-  do {                                 \
-    unsigned long __dummy;             \
-    __asm__ __volatile__(              \
-               "mov.l  1f, %0\n\t"     \
-               "or     %1, %0\n\t"     \
-               "jmp    @%0\n\t"        \
-               " nop\n\t"              \
-               ".balign 4\n"           \
-               "1:     .long 2f\n"     \
-               "2:"                    \
-               : "=&r" (__dummy)       \
-               : "r" (0x20000000));    \
-  } while (0)
-
-/*
- * Back to P1 area.
- */
-#define back_to_P1()                                   \
-  do {                                                 \
-    unsigned long __dummy;                             \
-    __asm__ __volatile__(                              \
-               "nop;nop;nop;nop;nop;nop;nop\n\t"       \
-               "mov.l  1f, %0\n\t"                     \
-               "jmp    @%0\n\t"                        \
-               " nop\n\t"                              \
-               ".balign 4\n"                           \
-               "1:     .long 2f\n"                     \
-               "2:"                                    \
-               : "=&r" (__dummy));                     \
-  } while (0)
+#include <asm/processor.h>
+#include <asm/system.h>
 
 #define CACHE_VALID       1
 #define CACHE_UPDATED     2
@@ -69,10 +17,10 @@ static inline void cache_wback_all(void)
 {
        unsigned long addr, data, i, j;
 
-       jump_to_P2();
-       for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++){
+       for (i = 0; i < CACHE_OC_NUM_ENTRIES; i++) {
                for (j = 0; j < CACHE_OC_NUM_WAYS; j++) {
-                       addr = CACHE_OC_ADDRESS_ARRAY | (j << CACHE_OC_WAY_SHIFT)
+                       addr = CACHE_OC_ADDRESS_ARRAY
+                               | (j << CACHE_OC_WAY_SHIFT)
                                | (i << CACHE_OC_ENTRY_SHIFT);
                        data = inl(addr);
                        if (data & CACHE_UPDATED) {
@@ -81,14 +29,12 @@ static inline void cache_wback_all(void)
                        }
                }
        }
-       back_to_P1();
 }
 
-
 #define CACHE_ENABLE      0
 #define CACHE_DISABLE     1
 
-int cache_control(unsigned int cmd)
+static int cache_control(unsigned int cmd)
 {
        unsigned long ccr;
 
@@ -107,18 +53,18 @@ int cache_control(unsigned int cmd)
        return 0;
 }
 
-void dcache_wback_range(u32 start, u32 end)
+void flush_dcache_range(unsigned long start, unsigned long end)
 {
        u32 v;
 
        start &= ~(L1_CACHE_BYTES - 1);
        for (v = start; v < end; v += L1_CACHE_BYTES) {
-               asm volatile ("ocbwb     %0" :  /* no output */
+               asm volatile ("ocbp     %0" :   /* no output */
                              : "m" (__m(v)));
        }
 }
 
-void dcache_invalid_range(u32 start, u32 end)
+void invalidate_dcache_range(unsigned long start, unsigned long end)
 {
        u32 v;
 
@@ -128,3 +74,36 @@ void dcache_invalid_range(u32 start, u32 end)
                              : "m" (__m(v)));
        }
 }
+
+void flush_cache(unsigned long addr, unsigned long size)
+{
+       flush_dcache_range(addr , addr + size);
+}
+
+void icache_enable(void)
+{
+       cache_control(CACHE_ENABLE);
+}
+
+void icache_disable(void)
+{
+       cache_control(CACHE_DISABLE);
+}
+
+int icache_status(void)
+{
+       return 0;
+}
+
+void dcache_enable(void)
+{
+}
+
+void dcache_disable(void)
+{
+}
+
+int dcache_status(void)
+{
+       return 0;
+}