#define CLKSTPCLR 0xFE0A0008
/* TMU */
-#define TSTR2 0xFE100004
-#define TCOR3 0xFE100008
-#define TCNT3 0xFE10000C
-#define TCR3 0xFE100010
-#define TCOR4 0xFE100014
-#define TCNT4 0xFE100018
-#define TCR4 0xFE10001C
-#define TOCR 0xFFD80000
-#define TSTR0 0xFFD80004
-#define TCOR0 0xFFD80008
-#define TCNT0 0xFFD8000C
-#define TCR0 0xFFD80010
-#define TCOR1 0xFFD80014
-#define TCNT1 0xFFD80018
-#define TCR1 0xFFD8001C
-#define TCOR2 0xFFD80020
-#define TCNT2 0xFFD80024
-#define TCR2 0xFFD80028
-#define TCPR2 0xFFD8002C
-#define TSTR TSTR0
+#define TMU_BASE 0xFFD80000
/* SCI */
#define SCSMR1 0xFFE00000
-#define SCBRR1 0xFFE00004
-#define SCSCR1 0xFFE00008
-#define SCTDR1 0xFFE0000C
-#define SCSSR1 0xFFE00010
-#define SCRDR1 0xFFE00014
-#define SCSCMR1 0xFFE00018
-#define SCSPTR1 0xFFE0001C
#define SCF0_BASE SCSMR1
/* SCIF */
#define SCSMR2 0xFFE80000
-#define SCBRR2 0xFFE80004
-#define SCSCR2 0xFFE80008
-#define SCFTDR2 0xFFE8000C
-#define SCFSR2 0xFFE80010
-#define SCFRDR2 0xFFE80014
-#define SCFCR2 0xFFE80018
-#define SCFDR2 0xFFE8001C
-#define SCSPTR2 0xFFE80020
-#define SCLSR2 0xFFE80024
#define SCIF1_BASE SCSMR2
/* H-UDI */