dm: replace dm_dbg() with pr_debug()

[u-boot] / arch / x86 / Kconfig

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 0cd981e73e43f7293a83f71ea2056ac185c0f1ff..38a618753a2a931e2599481867d6cf5e4b408e52 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -108,12 +108,14 @@ source "board/intel/Kconfig"
 
 # platform-specific options below
 source "arch/x86/cpu/baytrail/Kconfig"
+source "arch/x86/cpu/braswell/Kconfig"
 source "arch/x86/cpu/broadwell/Kconfig"
 source "arch/x86/cpu/coreboot/Kconfig"
 source "arch/x86/cpu/ivybridge/Kconfig"
 source "arch/x86/cpu/qemu/Kconfig"
 source "arch/x86/cpu/quark/Kconfig"
 source "arch/x86/cpu/queensbay/Kconfig"
+source "arch/x86/cpu/tangier/Kconfig"
 
 # architecture-specific options below
 
@@ -400,6 +402,15 @@ config FSP_BROKEN_HOB
          do not overwrite the important boot service data which is used by
          FSP, otherwise the subsequent call to fsp_notify() will fail.
 
+config FSP_LOCKDOWN_SPI
+       bool
+       depends on HAVE_FSP
+       help
+         Some Intel FSP (like Braswell) does SPI lock-down during the call
+         to fsp_notify(INIT_PHASE_BOOT). This option should be turned on
+         for such FSP and U-Boot will configure the SPI opcode registers
+         before the lock-down.
+
 config ENABLE_MRC_CACHE
        bool "Enable MRC cache"
        depends on !EFI && !SYS_COREBOOT
@@ -519,6 +530,13 @@ config AP_STACK_SIZE
          the memory used by this initialisation process. Typically 4KB is
          enough space.
 
+config CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
+       bool
+       help
+         This option indicates that the turbo mode setting is not package
+         scoped. i.e. turbo_enable() needs to be called on not just the
+         bootstrap processor (BSP).
+
 config HAVE_VGA_BIOS
        bool "Add a VGA BIOS image"
        help
@@ -541,6 +559,61 @@ config VGA_BIOS_ADDR
          address of 0xfff90000 indicates that the image will be put at offset
          0x90000 from the beginning of a 1MB flash device.
 
+config HAVE_VBT
+       bool "Add a Video BIOS Table (VBT) image"
+       depends on HAVE_FSP
+       help
+         Select this option if you have a Video BIOS Table (VBT) image that
+         you would like to add to your ROM. This is normally required if you
+         are using an Intel FSP firmware that is complaint with spec 1.1 or
+         later to initialize the integrated graphics device (IGD).
+
+         Video BIOS Table, or VBT, provides platform and board specific
+         configuration information to the driver that is not discoverable
+         or available through other means. By other means the most used
+         method here is to read EDID table from the attached monitor, over
+         Display Data Channel (DDC) using two pin I2C serial interface. VBT
+         configuration is related to display hardware and is available via
+         the ACPI OpRegion or, on older systems, in the PCI ROM (Option ROM).
+
+config VBT_FILE
+       string "Video BIOS Table (VBT) image filename"
+       depends on HAVE_VBT
+       default "vbt.bin"
+       help
+         The filename of the file to use as Video BIOS Table (VBT) image
+         in the board directory.
+
+config VBT_ADDR
+       hex "Video BIOS Table (VBT) image location"
+       depends on HAVE_VBT
+       default 0xfff90000
+       help
+         The location of Video BIOS Table (VBT) image in the SPI flash. For
+         example, base address of 0xfff90000 indicates that the image will
+         be put at offset 0x90000 from the beginning of a 1MB flash device.
+
+config VIDEO_FSP
+       bool "Enable FSP framebuffer driver support"
+       depends on HAVE_VBT && DM_VIDEO
+       help
+         Turn on this option to enable a framebuffer driver when U-Boot is
+         using Video BIOS Table (VBT) image for FSP firmware to initialize
+         the integrated graphics device.
+
+config ROM_TABLE_ADDR
+       hex
+       default 0xf0000
+       help
+         All x86 tables happen to like the address range from 0x0f0000
+         to 0x100000. We use 0xf0000 as the starting address to store
+         those tables, including PIRQ routing table, Multi-Processor
+         table and ACPI table.
+
+config ROM_TABLE_SIZE
+       hex
+       default 0x10000
+
 menu "System tables"
        depends on !EFI && !SYS_COREBOOT