Exynos542x: Add and enable get_periph_rate support

[u-boot] / arch / x86 / Kconfig

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index c2af607ca69b9e59299542fa8d63ca3ecb11c6ed..fef11f35528f4c830ade43d469d1e52ae89f6bac 100644 (file)
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -41,6 +41,30 @@ config TARGET_CROWNBAY
          Intel Platform Controller Hub EG20T, other system components and
          peripheral connectors for PCIe/SATA/USB/LAN/SD/UART/Audio/LVDS.
 
+config TARGET_MINNOWMAX
+       bool "Support Intel Minnowboard MAX"
+       help
+         This is the Intel Minnowboard MAX. It contains an Atom E3800
+         processor in a small form factor with Ethernet, micro-SD, USB 2,
+         USB 3, SATA, serial console, some GPIOs and HDMI 1.3 video out.
+         It requires some binary blobs - see README.x86 for details.
+
+         Note that PCIE_ECAM_BASE is set up by the FSP so the value used
+         by U-Boot matches that value.
+
+config TARGET_GALILEO
+       bool "Support Intel Galileo"
+       help
+         This is the Intel Galileo board, which is the first in a family of
+         Arduino-certified development and prototyping boards based on Intel
+         architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
+         single-core, single-thread, Intel Pentium processor instrunction set
+         architecture (ISA) compatible, operating at speeds up to 400Mhz,
+         along with 256MB DDR3 memory. It supports a wide range of industry
+         standard I/O interfaces, including a full-sized mini-PCIe slot,
+         one 100Mb Ethernet port, a microSD card slot, a USB host port and
+         a USB client port.
+
 endchoice
 
 config RAMBASE
@@ -324,26 +348,6 @@ config FRAMEBUFFER_VESA_MODE
 
 endmenu
 
-config TSC_CALIBRATION_BYPASS
-       bool "Bypass Time-Stamp Counter (TSC) calibration"
-       default n
-       help
-         By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
-         running frequency via Model-Specific Register (MSR) and Programmable
-         Interval Timer (PIT). If the calibration does not work on your board,
-         select this option and provide a hardcoded TSC running frequency with
-         CONFIG_TSC_FREQ_IN_MHZ below.
-
-         Normally this option should be turned on in a simulation environment
-         like qemu.
-
-config TSC_FREQ_IN_MHZ
-       int "Time-Stamp Counter (TSC) running frequency in MHz"
-       depends on TSC_CALIBRATION_BYPASS
-       default 1000
-       help
-         The running frequency in MHz of Time-Stamp Counter (TSC).
-
 config HAVE_FSP
        bool "Add an Firmware Support Package binary"
        help
@@ -382,21 +386,49 @@ config FSP_TEMP_RAM_ADDR
          Stack top address which is used in FspInit after DRAM is ready and
          CAR is disabled.
 
+source "arch/x86/cpu/baytrail/Kconfig"
+
 source "arch/x86/cpu/coreboot/Kconfig"
 
 source "arch/x86/cpu/ivybridge/Kconfig"
 
+source "arch/x86/cpu/quark/Kconfig"
+
 source "arch/x86/cpu/queensbay/Kconfig"
 
+config TSC_CALIBRATION_BYPASS
+       bool "Bypass Time-Stamp Counter (TSC) calibration"
+       default n
+       help
+         By default U-Boot automatically calibrates Time-Stamp Counter (TSC)
+         running frequency via Model-Specific Register (MSR) and Programmable
+         Interval Timer (PIT). If the calibration does not work on your board,
+         select this option and provide a hardcoded TSC running frequency with
+         CONFIG_TSC_FREQ_IN_MHZ below.
+
+         Normally this option should be turned on in a simulation environment
+         like qemu.
+
+config TSC_FREQ_IN_MHZ
+       int "Time-Stamp Counter (TSC) running frequency in MHz"
+       depends on TSC_CALIBRATION_BYPASS
+       default 1000
+       help
+         The running frequency in MHz of Time-Stamp Counter (TSC).
+
 source "board/coreboot/coreboot/Kconfig"
 
 source "board/google/chromebook_link/Kconfig"
 
 source "board/intel/crownbay/Kconfig"
 
+source "board/intel/minnowmax/Kconfig"
+
+source "board/intel/galileo/Kconfig"
+
 config PCIE_ECAM_BASE
        hex
-    default 0xe0000000
+       default 0xe0000000
        help
          This is the memory-mapped address of PCI configuration space, which
          is only available through the Enhanced Configuration Access