x86: quark: Configure MTRR to enable cache

[u-boot] / arch / x86 / cpu / baytrail / cpu.c

diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 05156a5a7b3cf8bcbeb0883ce5db900b98fea815..b1faf8ca32607e7da0e55df203b8cf954d44ce6b 100644 (file)
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -12,78 +12,9 @@
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
 #include <asm/lapic.h>
-#include <asm/mp.h>
 #include <asm/msr.h>
 #include <asm/turbo.h>
 
-#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
-       return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
-       MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
-       /* Wait for APs to finish initialization before proceeding. */
-       MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int detect_num_cpus(void)
-{
-       int ecx = 0;
-
-       /*
-        * Use the algorithm described in Intel 64 and IA-32 Architectures
-        * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
-        * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
-        * of CPUID Extended Topology Leaf.
-        */
-       while (1) {
-               struct cpuid_result leaf_b;
-
-               leaf_b = cpuid_ext(0xb, ecx);
-
-               /*
-                * Bay Trail doesn't have hyperthreading so just determine the
-                * number of cores by from level type (ecx[15:8] == * 2)
-                */
-               if ((leaf_b.ecx & 0xff00) == 0x0200)
-                       return leaf_b.ebx & 0xffff;
-               ecx++;
-       }
-}
-
-static int baytrail_init_cpus(void)
-{
-       struct mp_params mp_params;
-
-       lapic_setup();
-
-       mp_params.num_cpus = detect_num_cpus();
-       mp_params.parallel_microcode_load = 0,
-       mp_params.flight_plan = &mp_steps[0];
-       mp_params.num_records = ARRAY_SIZE(mp_steps);
-       mp_params.microcode_pointer = 0;
-
-       if (mp_init(&mp_params)) {
-               printf("Warning: MP init failure\n");
-               return -EIO;
-       }
-
-       return 0;
-}
-#endif
-
-int x86_init_cpus(void)
-{
-#ifdef CONFIG_SMP
-       debug("Init additional CPUs\n");
-       baytrail_init_cpus();
-#endif
-
-       return 0;
-}
-
 static void set_max_freq(void)
 {
        msr_t perf_ctl;
@@ -114,6 +45,8 @@ static void set_max_freq(void)
 
 static int cpu_x86_baytrail_probe(struct udevice *dev)
 {
+       if (!ll_boot_init())
+               return 0;
        debug("Init BayTrail core\n");
 
        /*
@@ -176,9 +109,38 @@ static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
        return 0;
 }
 
+static int baytrail_get_count(struct udevice *dev)
+{
+       int ecx = 0;
+
+       /*
+        * Use the algorithm described in Intel 64 and IA-32 Architectures
+        * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+        * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+        * of CPUID Extended Topology Leaf.
+        */
+       while (1) {
+               struct cpuid_result leaf_b;
+
+               leaf_b = cpuid_ext(0xb, ecx);
+
+               /*
+                * Bay Trail doesn't have hyperthreading so just determine the
+                * number of cores by from level type (ecx[15:8] == * 2)
+                */
+               if ((leaf_b.ecx & 0xff00) == 0x0200)
+                       return leaf_b.ebx & 0xffff;
+
+               ecx++;
+       }
+
+       return 0;
+}
+
 static const struct cpu_ops cpu_x86_baytrail_ops = {
        .get_desc       = cpu_x86_get_desc,
        .get_info       = baytrail_get_info,
+       .get_count      = baytrail_get_count,
 };
 
 static const struct udevice_id cpu_x86_baytrail_ids[] = {