x86: Refactor PCI to permit alternate init

[u-boot] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 14cb6994cfa787c3dd7265bb0b04ff5ad34f94a0..0760a61d84b8f083cea93823ccf27757edcf8d82 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -3,23 +3,7 @@
  * (C) Copyright 2008
  * Graeme Russ, graeme.russ@gmail.com.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -29,25 +13,26 @@
 #include <ns16550.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
+#include <asm/cpu.h>
 #include <asm/io.h>
+#include <asm/post.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
 #include <asm/arch/timestamp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/*
- * Miscellaneous platform dependent initializations
- */
-int cpu_init_f(void)
+int arch_cpu_init(void)
 {
        int ret = get_coreboot_info(&lib_sysinfo);
-       if (ret != 0)
+       if (ret != 0) {
                printf("Failed to parse coreboot tables.\n");
+               return ret;
+       }
 
        timestamp_init();
 
-       return ret;
+       return x86_cpu_init_f();
 }
 
 int board_early_init_f(void)
@@ -86,7 +71,12 @@ void show_boot_progress(int val)
                gd->arch.tsc_prev = now;
        }
 #endif
-       outb(val, 0x80);
+       outb(val, POST_PORT);
+}
+
+int print_cpuinfo(void)
+{
+       return default_print_cpuinfo();
 }
 
 int last_stage_init(void)
@@ -114,7 +104,7 @@ int board_eth_init(bd_t *bis)
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
-int board_final_cleanup(void)
+void board_final_cleanup(void)
 {
        /* Un-cache the ROM so the kernel has one
         * more MTRR available.
@@ -136,8 +126,6 @@ int board_final_cleanup(void)
        /* Issue SMI to Coreboot to lock down ME and registers */
        printf("Finalizing Coreboot\n");
        outb(0xcb, 0xb2);
-
-       return 0;
 }
 
 void panic_puts(const char *str)