x86: Refactor PCI to permit alternate init

[u-boot] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 4e1349f9508f9e09956818144cbba23ff3264fb9..0760a61d84b8f083cea93823ccf27757edcf8d82 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -13,7 +13,9 @@
 #include <ns16550.h>
 #include <asm/msr.h>
 #include <asm/cache.h>
+#include <asm/cpu.h>
 #include <asm/io.h>
+#include <asm/post.h>
 #include <asm/arch-coreboot/tables.h>
 #include <asm/arch-coreboot/sysinfo.h>
 #include <asm/arch/timestamp.h>
@@ -69,7 +71,12 @@ void show_boot_progress(int val)
                gd->arch.tsc_prev = now;
        }
 #endif
-       outb(val, 0x80);
+       outb(val, POST_PORT);
+}
+
+int print_cpuinfo(void)
+{
+       return default_print_cpuinfo();
 }
 
 int last_stage_init(void)
@@ -97,7 +104,7 @@ int board_eth_init(bd_t *bis)
 #define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
 #define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
 
-int board_final_cleanup(void)
+void board_final_cleanup(void)
 {
        /* Un-cache the ROM so the kernel has one
         * more MTRR available.
@@ -119,8 +126,6 @@ int board_final_cleanup(void)
        /* Issue SMI to Coreboot to lock down ME and registers */
        printf("Finalizing Coreboot\n");
        outb(0xcb, 0xb2);
-
-       return 0;
 }
 
 void panic_puts(const char *str)