SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / x86 / cpu / coreboot / coreboot.c

diff --git a/arch/x86/cpu/coreboot/coreboot.c b/arch/x86/cpu/coreboot/coreboot.c
index 2df72884f9232cb8203fb1f308f56829d58b1168..69025c1537ba780cc38aec88b5d926be1ef061d4 100644 (file)
--- a/arch/x86/cpu/coreboot/coreboot.c
+++ b/arch/x86/cpu/coreboot/coreboot.c
@@ -1,21 +1,15 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2008
  * Graeme Russ, graeme.russ@gmail.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
-#include <asm/u-boot-x86.h>
-#include <flash.h>
-#include <netdev.h>
-#include <ns16550.h>
-#include <asm/msr.h>
-#include <asm/cache.h>
-#include <asm/cpu.h>
+#include <fdtdec.h>
 #include <asm/io.h>
-#include <asm/arch/tables.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
 #include <asm/arch/sysinfo.h>
 #include <asm/arch/timestamp.h>
 
@@ -34,81 +28,59 @@ int arch_cpu_init(void)
        return x86_cpu_init_f();
 }
 
-int board_early_init_f(void)
+int checkcpu(void)
 {
        return 0;
 }
 
-int board_early_init_r(void)
-{
-       /* CPU Speed to 100MHz */
-       gd->cpu_clk = 100000000;
-
-       /* Crystal is 33.000MHz */
-       gd->bus_clk = 33000000;
-
-       return 0;
-}
-
 int print_cpuinfo(void)
 {
        return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-       if (gd->flags & GD_FLG_COLD_BOOT)
-               timestamp_add_to_bootstage();
-
-       return 0;
-}
-
-#ifndef CONFIG_SYS_NO_FLASH
-ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info)
+static void board_final_cleanup(void)
 {
-       return 0;
-}
-#endif
-
-int board_eth_init(bd_t *bis)
-{
-       return pci_eth_init(bis);
-}
-
-#define MTRR_TYPE_WP          5
-#define MTRRcap_MSR           0xfe
-#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
-#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
-
-void board_final_cleanup(void)
-{
-       /* Un-cache the ROM so the kernel has one
+       /*
+        * Un-cache the ROM so the kernel has one
         * more MTRR available.
         *
         * Coreboot should have assigned this to the
         * top available variable MTRR.
         */
-       u8 top_mtrr = (native_read_msr(MTRRcap_MSR) & 0xff) - 1;
-       u8 top_type = native_read_msr(MTRRphysBase_MSR(top_mtrr)) & 0xff;
+       u8 top_mtrr = (native_read_msr(MTRR_CAP_MSR) & 0xff) - 1;
+       u8 top_type = native_read_msr(MTRR_PHYS_BASE_MSR(top_mtrr)) & 0xff;
 
        /* Make sure this MTRR is the correct Write-Protected type */
-       if (top_type == MTRR_TYPE_WP) {
-               disable_caches();
-               wrmsrl(MTRRphysBase_MSR(top_mtrr), 0);
-               wrmsrl(MTRRphysMask_MSR(top_mtrr), 0);
-               enable_caches();
+       if (top_type == MTRR_TYPE_WRPROT) {
+               struct mtrr_state state;
+
+               mtrr_open(&state);
+               wrmsrl(MTRR_PHYS_BASE_MSR(top_mtrr), 0);
+               wrmsrl(MTRR_PHYS_MASK_MSR(top_mtrr), 0);
+               mtrr_close(&state);
        }
 
-       /* Issue SMI to Coreboot to lock down ME and registers */
-       printf("Finalizing Coreboot\n");
-       outb(0xcb, 0xb2);
+       if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
+               /*
+                * Issue SMI to coreboot to lock down ME and registers
+                * when allowed via device tree
+                */
+               printf("Finalizing coreboot\n");
+               outb(0xcb, 0xb2);
+       }
 }
 
-void panic_puts(const char *str)
+int last_stage_init(void)
 {
-       NS16550_t port = (NS16550_t)0x3f8;
+       if (gd->flags & GD_FLG_COLD_BOOT)
+               timestamp_add_to_bootstage();
+
+       board_final_cleanup();
+
+       return 0;
+}
 
-       NS16550_init(port, 1);
-       while (*str)
-               NS16550_putc(port, *str++);
+int misc_init_r(void)
+{
+       return 0;
 }