]> git.sur5r.net Git - u-boot/blobdiff - arch/x86/cpu/coreboot/coreboot.c
SPDX: Convert all of our single license tags to Linux Kernel style
[u-boot] / arch / x86 / cpu / coreboot / coreboot.c
index c3dfd28fffcac69ace0ce84aabf8de93c80790dd..69025c1537ba780cc38aec88b5d926be1ef061d4 100644 (file)
@@ -1,13 +1,12 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2011 The Chromium OS Authors.
  * (C) Copyright 2008
  * Graeme Russ, graeme.russ@gmail.com.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
-#include <netdev.h>
+#include <fdtdec.h>
 #include <asm/io.h>
 #include <asm/msr.h>
 #include <asm/mtrr.h>
@@ -29,7 +28,7 @@ int arch_cpu_init(void)
        return x86_cpu_init_f();
 }
 
-int board_early_init_f(void)
+int checkcpu(void)
 {
        return 0;
 }
@@ -39,20 +38,7 @@ int print_cpuinfo(void)
        return default_print_cpuinfo();
 }
 
-int last_stage_init(void)
-{
-       if (gd->flags & GD_FLG_COLD_BOOT)
-               timestamp_add_to_bootstage();
-
-       return 0;
-}
-
-int board_eth_init(bd_t *bis)
-{
-       return pci_eth_init(bis);
-}
-
-void board_final_cleanup(void)
+static void board_final_cleanup(void)
 {
        /*
         * Un-cache the ROM so the kernel has one
@@ -74,9 +60,24 @@ void board_final_cleanup(void)
                mtrr_close(&state);
        }
 
-       /* Issue SMI to Coreboot to lock down ME and registers */
-       printf("Finalizing Coreboot\n");
-       outb(0xcb, 0xb2);
+       if (!fdtdec_get_config_bool(gd->fdt_blob, "u-boot,no-apm-finalize")) {
+               /*
+                * Issue SMI to coreboot to lock down ME and registers
+                * when allowed via device tree
+                */
+               printf("Finalizing coreboot\n");
+               outb(0xcb, 0xb2);
+       }
+}
+
+int last_stage_init(void)
+{
+       if (gd->flags & GD_FLG_COLD_BOOT)
+               timestamp_add_to_bootstage();
+
+       board_final_cleanup();
+
+       return 0;
 }
 
 int misc_init_r(void)