Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[u-boot] / arch / x86 / cpu / coreboot / pci.c

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index c9983f15889e4cdab4a55c41973c8aaba530a287..67eb14ce99406dd90c6bb819715a9d94f8f2d4c5 100644 (file)
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -10,58 +10,38 @@
  */
 
 #include <common.h>
+#include <dm.h>
+#include <errno.h>
 #include <pci.h>
+#include <asm/io.h>
 #include <asm/pci.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
-                             struct pci_config_table *table)
-{
-       u8 secondary;
-       hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-       hose->last_busno = max(hose->last_busno, (int)secondary);
-       pci_hose_scan_bus(hose, secondary);
-}
-
-static struct pci_config_table pci_coreboot_config_table[] = {
-       /* vendor, device, class, bus, dev, func */
-       { PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_BRIDGE_PCI,
-               PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, &config_pci_bridge },
-       {}
+static const struct dm_pci_ops pci_x86_ops = {
+       .read_config    = pci_x86_read_config,
+       .write_config   = pci_x86_write_config,
 };
 
-void board_pci_setup_hose(struct pci_controller *hose)
-{
-       hose->config_table = pci_coreboot_config_table;
-       hose->first_busno = 0;
-       hose->last_busno = 0;
-
-       /* PCI memory space */
-       pci_set_region(hose->regions + 0,
-                      CONFIG_PCI_MEM_BUS,
-                      CONFIG_PCI_MEM_PHYS,
-                      CONFIG_PCI_MEM_SIZE,
-                      PCI_REGION_MEM);
-
-       /* PCI IO space */
-       pci_set_region(hose->regions + 1,
-                      CONFIG_PCI_IO_BUS,
-                      CONFIG_PCI_IO_PHYS,
-                      CONFIG_PCI_IO_SIZE,
-                      PCI_REGION_IO);
+static const struct udevice_id pci_x86_ids[] = {
+       { .compatible = "pci-x86" },
+       { }
+};
 
-       pci_set_region(hose->regions + 2,
-                      CONFIG_PCI_PREF_BUS,
-                      CONFIG_PCI_PREF_PHYS,
-                      CONFIG_PCI_PREF_SIZE,
-                      PCI_REGION_PREFETCH);
+U_BOOT_DRIVER(pci_x86_drv) = {
+       .name           = "pci_x86",
+       .id             = UCLASS_PCI,
+       .of_match       = pci_x86_ids,
+       .ops            = &pci_x86_ops,
+};
 
-       pci_set_region(hose->regions + 3,
-                      0,
-                      0,
-                      gd->ram_size,
-                      PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
+static const struct udevice_id generic_pch_ids[] = {
+       { .compatible = "intel,pch" },
+       { }
+};
 
-       hose->region_count = 4;
-}
+U_BOOT_DRIVER(generic_pch_drv) = {
+       .name           = "pch",
+       .id             = UCLASS_PCH,
+       .of_match       = generic_pch_ids,
+};