Merge git://git.denx.de/u-boot-x86

[u-boot] / arch / x86 / cpu / coreboot / pci.c

diff --git a/arch/x86/cpu/coreboot/pci.c b/arch/x86/cpu/coreboot/pci.c
index 8f941674806ce749087a0d678abfe2aa3c131dd4..6a3dd9391432017898e85c714100ee8e53232ce2 100644 (file)
--- a/arch/x86/cpu/coreboot/pci.c
+++ b/arch/x86/cpu/coreboot/pci.c
@@ -6,37 +6,19 @@
  * (C) Copyright 2002
  * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <pci.h>
 #include <asm/pci.h>
 
-static struct pci_controller coreboot_hose;
-
 static void config_pci_bridge(struct pci_controller *hose, pci_dev_t dev,
                              struct pci_config_table *table)
 {
        u8 secondary;
        hose->read_byte(hose, dev, PCI_SECONDARY_BUS, &secondary);
-       hose->last_busno = max(hose->last_busno, secondary);
+       hose->last_busno = max(hose->last_busno, (int)secondary);
        pci_hose_scan_bus(hose, secondary);
 }
 
@@ -47,19 +29,13 @@ static struct pci_config_table pci_coreboot_config_table[] = {
        {}
 };
 
-void pci_init_board(void)
+void board_pci_setup_hose(struct pci_controller *hose)
 {
-       coreboot_hose.config_table = pci_coreboot_config_table;
-       coreboot_hose.first_busno = 0;
-       coreboot_hose.last_busno = 0;
-
-       pci_set_region(coreboot_hose.regions + 0, 0x0, 0x0, 0xffffffff,
-               PCI_REGION_MEM);
-       coreboot_hose.region_count = 1;
-
-       pci_setup_type1(&coreboot_hose);
-
-       pci_register_hose(&coreboot_hose);
+       hose->config_table = pci_coreboot_config_table;
+       hose->first_busno = 0;
+       hose->last_busno = 0;
 
-       pci_hose_scan(&coreboot_hose);
+       pci_set_region(hose->regions + 0, 0x0, 0x0, 0xffffffff,
+                      PCI_REGION_MEM);
+       hose->region_count = 1;
 }