x86: quark: Add USB PHY initialization support

[u-boot] / arch / x86 / cpu / cpu.c

diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c
index d108ee5c4e25538bc60314f19d03e83caf0837fc..1b76ca117ee3df339d981bfe3cde74cbd4a9ee9d 100644 (file)
--- a/arch/x86/cpu/cpu.c
+++ b/arch/x86/cpu/cpu.c
@@ -28,6 +28,8 @@
 #include <asm/cpu.h>
 #include <asm/lapic.h>
 #include <asm/mp.h>
+#include <asm/msr.h>
+#include <asm/mtrr.h>
 #include <asm/post.h>
 #include <asm/processor.h>
 #include <asm/processor-flags.h>
@@ -134,9 +136,12 @@ static void load_gdt(const u64 *boot_gdt, u16 num_entries)
        asm volatile("lgdtl %0\n" : : "m" (gdt));
 }
 
-void setup_gdt(gd_t *id, u64 *gdt_addr)
+void arch_setup_gd(gd_t *new_gd)
 {
-       id->arch.gdt = gdt_addr;
+       u64 *gdt_addr;
+
+       gdt_addr = new_gd->arch.gdt;
+
        /* CS: code, read/execute, 4 GB, base 0 */
        gdt_addr[X86_GDT_ENTRY_32BIT_CS] = GDT_ENTRY(0xc09b, 0, 0xfffff);
 
@@ -144,9 +149,9 @@ void setup_gdt(gd_t *id, u64 *gdt_addr)
        gdt_addr[X86_GDT_ENTRY_32BIT_DS] = GDT_ENTRY(0xc093, 0, 0xfffff);
 
        /* FS: data, read/write, 4 GB, base (Global Data Pointer) */
-       id->arch.gd_addr = id;
+       new_gd->arch.gd_addr = new_gd;
        gdt_addr[X86_GDT_ENTRY_32BIT_FS] = GDT_ENTRY(0xc093,
-                    (ulong)&id->arch.gd_addr, 0xfffff);
+                    (ulong)&new_gd->arch.gd_addr, 0xfffff);
 
        /* 16-bit CS: code, read/execute, 64 kB, base 0 */
        gdt_addr[X86_GDT_ENTRY_16BIT_CS] = GDT_ENTRY(0x009b, 0, 0x0ffff);
@@ -328,13 +333,15 @@ int x86_cpu_init_f(void)
        const u32 em_rst = ~X86_CR0_EM;
        const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE;
 
-       /* initialize FPU, reset EM, set MP and NE */
-       asm ("fninit\n" \
-            "movl %%cr0, %%eax\n" \
-            "andl %0, %%eax\n" \
-            "orl  %1, %%eax\n" \
-            "movl %%eax, %%cr0\n" \
-            : : "i" (em_rst), "i" (mp_ne_set) : "eax");
+       if (ll_boot_init()) {
+               /* initialize FPU, reset EM, set MP and NE */
+               asm ("fninit\n" \
+               "movl %%cr0, %%eax\n" \
+               "andl %0, %%eax\n" \
+               "orl  %1, %%eax\n" \
+               "movl %%eax, %%cr0\n" \
+               : : "i" (em_rst), "i" (mp_ne_set) : "eax");
+       }
 
        /* identify CPU via cpuid and store the decoded info into gd->arch */
        if (has_cpuid()) {
@@ -351,6 +358,41 @@ int x86_cpu_init_f(void)
 
                gd->arch.has_mtrr = has_mtrr();
        }
+       /* Don't allow PCI region 3 to use memory in the 2-4GB memory hole */
+       gd->pci_ram_top = 0x80000000U;
+
+       /* Configure fixed range MTRRs for some legacy regions */
+       if (gd->arch.has_mtrr) {
+               u64 mtrr_cap;
+
+               mtrr_cap = native_read_msr(MTRR_CAP_MSR);
+               if (mtrr_cap & MTRR_CAP_FIX) {
+                       /* Mark the VGA RAM area as uncacheable */
+                       native_write_msr(MTRR_FIX_16K_A0000_MSR,
+                                        MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE),
+                                        MTRR_FIX_TYPE(MTRR_TYPE_UNCACHEABLE));
+
+                       /*
+                        * Mark the PCI ROM area as cacheable to improve ROM
+                        * execution performance.
+                        */
+                       native_write_msr(MTRR_FIX_4K_C0000_MSR,
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+                       native_write_msr(MTRR_FIX_4K_C8000_MSR,
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+                       native_write_msr(MTRR_FIX_4K_D0000_MSR,
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+                       native_write_msr(MTRR_FIX_4K_D8000_MSR,
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK),
+                                        MTRR_FIX_TYPE(MTRR_TYPE_WRBACK));
+
+                       /* Enable the fixed range MTRRs */
+                       msr_setbits_64(MTRR_DEF_TYPE_MSR, MTRR_DEF_TYPE_FIX_EN);
+               }
+       }
 
        return 0;
 }
@@ -419,7 +461,7 @@ void x86_full_reset(void)
 
 int dcache_status(void)
 {
-       return !(read_cr0() & 0x40000000);
+       return !(read_cr0() & X86_CR0_CD);
 }
 
 /* Define these functions to allow ehch-hcd to function */
@@ -659,6 +701,15 @@ __weak int x86_init_cpus(void)
 #ifdef CONFIG_SMP
        debug("Init additional CPUs\n");
        x86_mp_init();
+#else
+       struct udevice *dev;
+
+       /*
+        * This causes the cpu-x86 driver to be probed.
+        * We don't check return value here as we want to allow boards
+        * which have not been converted to use cpu uclass driver to boot.
+        */
+       uclass_first_device(UCLASS_CPU, &dev);
 #endif
 
        return 0;
@@ -666,5 +717,8 @@ __weak int x86_init_cpus(void)
 
 int cpu_init_r(void)
 {
-       return x86_init_cpus();
+       if (ll_boot_init())
+               return x86_init_cpus();
+
+       return 0;
 }