Merge branch 'master' of git://git.denx.de/u-boot-i2c; branch 'master' of git://git...

[u-boot] / arch / x86 / cpu / ivybridge / Kconfig

diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index afca9579da29065bab64312c429b6a073039311f..1768a26a35293cb840cfb54f5565c174ef65d1a0 100644 (file)
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -5,58 +5,13 @@
 #
 # SPDX-License-Identifier:     GPL-2.0
 
-
-config NORTHBRIDGE_INTEL_SANDYBRIDGE
-       bool
-       select CACHE_MRC_BIN
-       select CPU_INTEL_MODEL_206AX
-
 config NORTHBRIDGE_INTEL_IVYBRIDGE
        bool
        select CACHE_MRC_BIN
-       select CPU_INTEL_MODEL_306AX
-
-if NORTHBRIDGE_INTEL_SANDYBRIDGE
-
-config VGA_BIOS_ID
-       string
-       default "8086,0106"
-
-config CACHE_MRC_SIZE_KB
-       int
-       default 256
-
-config MRC_CACHE_BASE
-       hex
-       default 0xff800000
-
-config MRC_CACHE_LOCATION
-       hex
-       depends on !CHROMEOS
-       default 0x1ec000
-
-config MRC_CACHE_SIZE
-       hex
-       depends on !CHROMEOS
-       default 0x10000
-
-config DCACHE_RAM_BASE
-       hex
-       default 0xff7f0000
-
-config DCACHE_RAM_SIZE
-       hex
-       default 0x10000
-
-endif
 
 if NORTHBRIDGE_INTEL_IVYBRIDGE
 
-config VGA_BIOS_ID
-       string
-       default "8086,0166"
-
-config EXTERNAL_MRC_BLOB
+config CACHE_MRC_BIN
        bool
        default n
 
@@ -64,20 +19,6 @@ config CACHE_MRC_SIZE_KB
        int
        default 512
 
-config MRC_CACHE_BASE
-       hex
-       default 0xff800000
-
-config MRC_CACHE_LOCATION
-       hex
-       depends on !CHROMEOS
-       default 0x370000
-
-config MRC_CACHE_SIZE
-       hex
-       depends on !CHROMEOS
-       default 0x10000
-
 config DCACHE_RAM_BASE
        hex
        default 0xff7e0000
@@ -86,10 +27,6 @@ config DCACHE_RAM_SIZE
        hex
        default 0x20000
 
-endif
-
-if NORTHBRIDGE_INTEL_SANDYBRIDGE || NORTHBRIDGE_INTEL_IVYBRIDGE
-
 config HAVE_MRC
         bool "Add a System Agent binary"
         help
@@ -108,27 +45,9 @@ config DCACHE_RAM_MRC_VAR_SIZE
          memory reference code. This should be set to 16KB (0x4000 hex)
          so that MRC has enough space to run.
 
-config MRC_FILE
-       string "Intel System Agent path and filename"
-       depends on HAVE_MRC
-       default "systemagent-ivybridge.bin" if NORTHBRIDGE_INTEL_IVYBRIDGE
-       default "systemagent-sandybridge.bin" if NORTHBRIDGE_INTEL_SANDYBRIDGE
-       help
-         The path and filename of the file to use as System Agent
-         binary.
-
 config CPU_SPECIFIC_OPTIONS
        def_bool y
        select SMM_TSEG
-       select ARCH_BOOTBLOCK_X86_32
-       select ARCH_ROMSTAGE_X86_32
-       select ARCH_RAMSTAGE_X86_32
-       select SMP
-       select SSE2
-       select UDELAY_LAPIC
-       select CPU_MICROCODE_IN_CBFS
-       select TSC_SYNC_MFENCE
-       select HAVE_INTEL_ME
        select X86_RAMTEST
 
 config SMM_TSEG_SIZE
@@ -153,20 +72,3 @@ config ENABLE_VMX
          slowly.
 
 endif
-
-config CPU_INTEL_SOCKET_RPGA989
-       bool
-
-if CPU_INTEL_SOCKET_RPGA989
-
-config SOCKET_SPECIFIC_OPTIONS # dummy
-       def_bool y
-       select MMX
-       select SSE
-       select CACHE_AS_RAM
-
-config CACHE_MRC_BIN
-       bool
-       default n
-
-endif