Merge git://git.denx.de/u-boot-net

[u-boot] / arch / x86 / cpu / ivybridge / cpu.c

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c
index e9253100f6e051987ad6995e49836a5c0e0d3b68..343bfb4e98e264a7e5fa91f7e9f58c89427f73f3 100644 (file)
--- a/arch/x86/cpu/ivybridge/cpu.c
+++ b/arch/x86/cpu/ivybridge/cpu.c
@@ -12,6 +12,7 @@
  */
 
 #include <common.h>
+#include <dm.h>
 #include <errno.h>
 #include <fdtdec.h>
 #include <asm/cpu.h>
@@ -91,7 +92,7 @@ static int set_flex_ratio_to_tdp_nominal(void)
 
        /* Issue warm reset, will be "CPU only" due to soft reset data */
        outb(0x0, PORT_RESET);
-       outb(0x6, PORT_RESET);
+       outb(SYS_RST | RST_CPU, PORT_RESET);
        cpu_hlt();
 
        /* Not reached */
@@ -115,24 +116,32 @@ static void set_spi_speed(void)
 }
 
 int arch_cpu_init(void)
+{
+       post_code(POST_CPU_INIT);
+
+       return x86_cpu_init_f();
+}
+
+int arch_cpu_init_dm(void)
 {
        const void *blob = gd->fdt_blob;
        struct pci_controller *hose;
+       struct udevice *bus;
        int node;
        int ret;
 
-       post_code(POST_CPU_INIT);
-       timer_set_base(rdtsc());
-
-       ret = x86_cpu_init_f();
+       post_code(0x70);
+       ret = uclass_get_device(UCLASS_PCI, 0, &bus);
+       post_code(0x71);
        if (ret)
                return ret;
+       post_code(0x72);
+       hose = dev_get_uclass_priv(bus);
 
-       ret = pci_early_init_hose(&hose);
-       if (ret)
-               return ret;
+       /* TODO(sjg@chromium.org): Get rid of gd->hose */
+       gd->hose = hose;
 
-       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_LPC);
+       node = fdtdec_next_compatible(blob, 0, COMPAT_INTEL_PCH);
        if (node < 0)
                return -ENOENT;
        ret = lpc_early_init(gd->fdt_blob, node, PCH_LPC_DEV);
@@ -167,21 +176,21 @@ static int enable_smbus(void)
        dev = PCI_BDF(0x0, 0x1f, 0x3);
 
        /* Check to make sure we've got the right device. */
-       value = pci_read_config16(dev, 0x0);
+       value = x86_pci_read_config16(dev, 0x0);
        if (value != 0x8086) {
                printf("SMBus controller not found\n");
                return -ENOSYS;
        }
 
        /* Set SMBus I/O base. */
-       pci_write_config32(dev, SMB_BASE,
-                          SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+       x86_pci_write_config32(dev, SMB_BASE,
+                              SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
 
        /* Set SMBus enable. */
-       pci_write_config8(dev, HOSTC, HST_EN);
+       x86_pci_write_config8(dev, HOSTC, HST_EN);
 
        /* Set SMBus I/O space enable. */
-       pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+       x86_pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
 
        /* Disable interrupt generation. */
        outb(0, SMBUS_IO_BASE + SMBHSTCTL);
@@ -214,25 +223,25 @@ static void enable_usb_bar(void)
        u32 cmd;
 
        /* USB Controller 1 */
-       pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
-                          PCH_EHCI0_TEMP_BAR0);
-       cmd = pci_read_config32(usb0, PCI_COMMAND);
+       x86_pci_write_config32(usb0, PCI_BASE_ADDRESS_0,
+                              PCH_EHCI0_TEMP_BAR0);
+       cmd = x86_pci_read_config32(usb0, PCI_COMMAND);
        cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-       pci_write_config32(usb0, PCI_COMMAND, cmd);
+       x86_pci_write_config32(usb0, PCI_COMMAND, cmd);
 
        /* USB Controller 1 */
-       pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
-                          PCH_EHCI1_TEMP_BAR0);
-       cmd = pci_read_config32(usb1, PCI_COMMAND);
+       x86_pci_write_config32(usb1, PCI_BASE_ADDRESS_0,
+                              PCH_EHCI1_TEMP_BAR0);
+       cmd = x86_pci_read_config32(usb1, PCI_COMMAND);
        cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-       pci_write_config32(usb1, PCI_COMMAND, cmd);
+       x86_pci_write_config32(usb1, PCI_COMMAND, cmd);
 
        /* USB3 Controller */
-       pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
-                          PCH_XHCI_TEMP_BAR0);
-       cmd = pci_read_config32(usb3, PCI_COMMAND);
+       x86_pci_write_config32(usb3, PCI_BASE_ADDRESS_0,
+                              PCH_XHCI_TEMP_BAR0);
+       cmd = x86_pci_read_config32(usb3, PCI_COMMAND);
        cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
-       pci_write_config32(usb3, PCI_COMMAND, cmd);
+       x86_pci_write_config32(usb3, PCI_COMMAND, cmd);
 }
 
 static int report_bist_failure(void)
@@ -276,8 +285,7 @@ int print_cpuinfo(void)
 
                /* System is not happy after keyboard reset... */
                debug("Issuing CF9 warm reset\n");
-               outb(0x6, 0xcf9);
-               cpu_hlt();
+               reset_cpu(0);
        }
 
        /* Early chipset init required before RAM init can work */
@@ -290,16 +298,7 @@ int print_cpuinfo(void)
        pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT);
 
        if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
-               debug("Resume from S3 detected.\n");
-               boot_mode = PEI_BOOT_RESUME;
-               /* Clear SLP_TYPE. This will break stage2 but
-                * we care for that when we get there.
-                */
-               outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT);
-#else
                debug("Resume from S3 detected, but disabled.\n");
-#endif
        } else {
                /*
                 * TODO: An indication of life might be possible here (e.g.
@@ -320,8 +319,8 @@ int print_cpuinfo(void)
        gd->arch.pei_boot_mode = boot_mode;
 
        /* TODO: Move this to the board or driver */
-       pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
-       pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
+       x86_pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1);
+       x86_pci_write_config32(PCH_LPC_DEV, GPIO_CNTL, 0x10);
 
        /* Print processor name */
        name = cpu_get_name(processor_name);
@@ -331,3 +330,10 @@ int print_cpuinfo(void)
 
        return 0;
 }
+
+void board_debug_uart_init(void)
+{
+       /* This enables the debug UART */
+       pci_x86_write_config(NULL, PCH_LPC_DEV, LPC_EN, COMA_LPC_EN,
+                            PCI_SIZE_16);
+}