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[u-boot] / arch / x86 / cpu / ivybridge / model_206ax.c

diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c
index 9654600cf17866708698a3347a9fa6f7720ebec3..81dedee2ec097125c86fdc85e0538cc7dbae45b8 100644 (file)
--- a/arch/x86/cpu/ivybridge/model_206ax.c
+++ b/arch/x86/cpu/ivybridge/model_206ax.c
@@ -12,18 +12,18 @@
 #include <dm.h>
 #include <fdtdec.h>
 #include <malloc.h>
-#include <asm/acpi.h>
 #include <asm/cpu.h>
 #include <asm/cpu_x86.h>
-#include <asm/lapic.h>
 #include <asm/msr.h>
+#include <asm/msr-index.h>
 #include <asm/mtrr.h>
 #include <asm/processor.h>
 #include <asm/speedstep.h>
 #include <asm/turbo.h>
-#include <asm/arch/bd82x6x.h>
 #include <asm/arch/model_206ax.h>
 
+DECLARE_GLOBAL_DATA_PTR;
+
 static void enable_vmx(void)
 {
        struct cpuid_result regs;
@@ -288,8 +288,8 @@ static int configure_thermal_target(struct udevice *dev)
        int tcc_offset;
        msr_t msr;
 
-       tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
-                                   0);
+       tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+                                   "tcc-offset", 0);
 
        /* Set TCC activaiton offset if supported */
        msr = msr_read(MSR_PLATFORM_INFO);
@@ -363,7 +363,7 @@ static void set_max_ratio(void)
                msr = msr_read(MSR_PLATFORM_INFO);
                perf_ctl.lo = msr.lo & 0xff00;
        }
-       msr_write(IA32_PERF_CTL, perf_ctl);
+       msr_write(MSR_IA32_PERF_CTL, perf_ctl);
 
        debug("model_x06ax: frequency set to %d\n",
              ((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
@@ -418,7 +418,6 @@ static int model_206ax_init(struct udevice *dev)
 
        /* Enable the local cpu apics */
        enable_lapic_tpr();
-       lapic_setup();
 
        /* Enable virtualization if enabled in CMOS */
        enable_vmx();
@@ -455,9 +454,10 @@ static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
 {
        msr_t msr;
 
-       msr = msr_read(IA32_PERF_CTL);
+       msr = msr_read(MSR_IA32_PERF_CTL);
        info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
-       info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+       info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+               1 << CPU_FEAT_UCODE;
 
        return 0;
 }
@@ -479,6 +479,7 @@ static const struct cpu_ops cpu_x86_model_206ax_ops = {
        .get_desc       = cpu_x86_get_desc,
        .get_info       = model_206ax_get_info,
        .get_count      = model_206ax_get_count,
+       .get_vendor     = cpu_x86_get_vendor,
 };
 
 static const struct udevice_id cpu_x86_model_206ax_ids[] = {