#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
-#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
-#include <asm/lapic.h>
#include <asm/msr.h>
+#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
-#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static void enable_vmx(void)
{
struct cpuid_result regs;
int tcc_offset;
msr_t msr;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "tcc-offset",
- 0);
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "tcc-offset", 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
msr = msr_read(MSR_PLATFORM_INFO);
perf_ctl.lo = msr.lo & 0xff00;
}
- msr_write(IA32_PERF_CTL, perf_ctl);
+ msr_write(MSR_IA32_PERF_CTL, perf_ctl);
debug("model_x06ax: frequency set to %d\n",
((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
/* Enable the local cpu apics */
enable_lapic_tpr();
- lapic_setup();
/* Enable virtualization if enabled in CMOS */
enable_vmx();
{
msr_t msr;
- msr = msr_read(IA32_PERF_CTL);
+ msr = msr_read(MSR_IA32_PERF_CTL);
info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
- info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+ info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+ 1 << CPU_FEAT_UCODE;
return 0;
}
.get_desc = cpu_x86_get_desc,
.get_info = model_206ax_get_info,
.get_count = model_206ax_get_count,
+ .get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_model_206ax_ids[] = {