#include <dm.h>
#include <fdtdec.h>
#include <malloc.h>
-#include <asm/acpi.h>
#include <asm/cpu.h>
#include <asm/cpu_x86.h>
-#include <asm/lapic.h>
#include <asm/msr.h>
+#include <asm/msr-index.h>
#include <asm/mtrr.h>
#include <asm/processor.h>
#include <asm/speedstep.h>
#include <asm/turbo.h>
-#include <asm/arch/bd82x6x.h>
#include <asm/arch/model_206ax.h>
+DECLARE_GLOBAL_DATA_PTR;
+
static void enable_vmx(void)
{
struct cpuid_result regs;
msr_write(MSR_PP1_CURRENT_CONFIG, msr);
}
-static int configure_thermal_target(void)
+static int configure_thermal_target(struct udevice *dev)
{
int tcc_offset;
msr_t msr;
- int node;
- /* Find pointer to CPU configuration */
- node = fdtdec_next_compatible(gd->fdt_blob, 0,
- COMPAT_INTEL_MODEL_206AX);
- if (node < 0)
- return -ENOENT;
- tcc_offset = fdtdec_get_int(gd->fdt_blob, node, "tcc-offset", 0);
+ tcc_offset = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
+ "tcc-offset", 0);
/* Set TCC activaiton offset if supported */
msr = msr_read(MSR_PLATFORM_INFO);
msr = msr_read(MSR_PLATFORM_INFO);
perf_ctl.lo = msr.lo & 0xff00;
}
- msr_write(IA32_PERF_CTL, perf_ctl);
+ msr_write(MSR_IA32_PERF_CTL, perf_ctl);
debug("model_x06ax: frequency set to %d\n",
((perf_ctl.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK);
static unsigned ehci_debug_addr;
#endif
-int model_206ax_init(struct x86_cpu_priv *cpu)
+static int model_206ax_init(struct udevice *dev)
{
int ret;
set_ehci_debug(0);
#endif
- /* Setup MTRRs based on physical address size */
-#if 0 /* TODO: Implement this */
- struct cpuid_result cpuid_regs;
-
- cpuid_regs = cpuid(0x80000008);
- x86_setup_fixed_mtrrs();
- x86_setup_var_mtrrs(cpuid_regs.eax & 0xff, 2);
- x86_mtrr_check();
-#endif
-
#if CONFIG_USBDEBUG
set_ehci_debug(ehci_debug_addr);
#endif
/* Enable the local cpu apics */
enable_lapic_tpr();
- lapic_setup();
/* Enable virtualization if enabled in CMOS */
enable_vmx();
configure_misc();
/* Thermal throttle activation offset */
- ret = configure_thermal_target();
+ ret = configure_thermal_target(dev);
if (ret) {
debug("Cannot set thermal target\n");
return ret;
static int model_206ax_get_info(struct udevice *dev, struct cpu_info *info)
{
- info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU;
+ msr_t msr;
+
+ msr = msr_read(MSR_IA32_PERF_CTL);
+ info->cpu_freq = ((msr.lo >> 8) & 0xff) * SANDYBRIDGE_BCLK * 1000000;
+ info->features = 1 << CPU_FEAT_L1_CACHE | 1 << CPU_FEAT_MMU |
+ 1 << CPU_FEAT_UCODE;
return 0;
}
static int cpu_x86_model_206ax_probe(struct udevice *dev)
{
+ if (dev->seq == 0)
+ model_206ax_init(dev);
+
return 0;
}
.get_desc = cpu_x86_get_desc,
.get_info = model_206ax_get_info,
.get_count = model_206ax_get_count,
+ .get_vendor = cpu_x86_get_vendor,
};
static const struct udevice_id cpu_x86_model_206ax_ids[] = {