SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / x86 / cpu / quark / msg_port.c

diff --git a/arch/x86/cpu/quark/msg_port.c b/arch/x86/cpu/quark/msg_port.c
index 31713e321f2cf6c02e8b80f2458c38491d642fed..d4f8c082ffc2f4dee041e753fb61c4ff7bb89207 100644 (file)
--- a/arch/x86/cpu/quark/msg_port.c
+++ b/arch/x86/cpu/quark/msg_port.c
@@ -1,38 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
-#include <pci.h>
 #include <asm/arch/device.h>
 #include <asm/arch/msg_port.h>
+#include <asm/arch/quark.h>
 
 void msg_port_setup(int op, int port, int reg)
 {
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
-                              (((op) << 24) | ((port) << 16) |
-                              (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_REG,
+                                  (((op) << 24) | ((port) << 16) |
+                                  (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
 }
 
 u32 msg_port_read(u8 port, u32 reg)
 {
        u32 value;
 
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-                              reg & 0xffffff00);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+                                  reg & 0xffffff00);
        msg_port_setup(MSG_OP_READ, port, reg);
-       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+       qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
 
        return value;
 }
 
 void msg_port_write(u8 port, u32 reg, u32 value)
 {
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-                              reg & 0xffffff00);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+                                  reg & 0xffffff00);
        msg_port_setup(MSG_OP_WRITE, port, reg);
 }
 
@@ -40,19 +39,19 @@ u32 msg_port_alt_read(u8 port, u32 reg)
 {
        u32 value;
 
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-                              reg & 0xffffff00);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+                                  reg & 0xffffff00);
        msg_port_setup(MSG_OP_ALT_READ, port, reg);
-       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+       qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
 
        return value;
 }
 
 void msg_port_alt_write(u8 port, u32 reg, u32 value)
 {
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-                              reg & 0xffffff00);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+                                  reg & 0xffffff00);
        msg_port_setup(MSG_OP_ALT_WRITE, port, reg);
 }
 
@@ -60,18 +59,18 @@ u32 msg_port_io_read(u8 port, u32 reg)
 {
        u32 value;
 
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-                              reg & 0xffffff00);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+                                  reg & 0xffffff00);
        msg_port_setup(MSG_OP_IO_READ, port, reg);
-       pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
+       qrk_pci_read_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, &value);
 
        return value;
 }
 
 void msg_port_io_write(u8 port, u32 reg, u32 value)
 {
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
-       pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
-                              reg & 0xffffff00);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_DATA_REG, value);
+       qrk_pci_write_config_dword(QUARK_HOST_BRIDGE, MSG_CTRL_EXT_REG,
+                                  reg & 0xffffff00);
        msg_port_setup(MSG_OP_IO_WRITE, port, reg);
 }