x86: Set APs' req_seq to the reg number from device tree

[u-boot] / arch / x86 / cpu / queensbay / tnc.c

diff --git a/arch/x86/cpu/queensbay/tnc.c b/arch/x86/cpu/queensbay/tnc.c
index 873de7be9ddf7f7c565f5ed8f6f0c9e5aee6304c..c4656422e15ec0c51826a4541d853208edef6b38 100644 (file)
--- a/arch/x86/cpu/queensbay/tnc.c
+++ b/arch/x86/cpu/queensbay/tnc.c
@@ -25,7 +25,6 @@ static void unprotect_spi_flash(void)
 
 int arch_cpu_init(void)
 {
-       struct pci_controller *hose;
        int ret;
 
        post_code(POST_CPU_INIT);
@@ -37,10 +36,6 @@ int arch_cpu_init(void)
        if (ret)
                return ret;
 
-       ret = pci_early_init_hose(&hose);
-       if (ret)
-               return ret;
-
        unprotect_spi_flash();
 
        return 0;
@@ -69,22 +64,21 @@ void cpu_irq_init(void)
         * Route TunnelCreek PCI device interrupt pin to PIRQ
         *
         * Since PCIe downstream ports received INTx are routed to PIRQ
-        * A/B/C/D directly and not configurable, we route internal PCI
-        * device's INTx to PIRQ E/F/G/H.
+        * A/B/C/D directly and not configurable, we have to route PCIe
+        * root ports' INTx to PIRQ A/B/C/D as well. For other devices
+        * on TunneCreek, route them to PIRQ E/F/G/H.
         */
        writew(PIRQE, &rcba->d02ir);
        writew(PIRQF, &rcba->d03ir);
        writew(PIRQG, &rcba->d27ir);
        writew(PIRQH, &rcba->d31ir);
-       writew(PIRQE, &rcba->d23ir);
-       writew(PIRQF, &rcba->d24ir);
-       writew(PIRQG, &rcba->d25ir);
-       writew(PIRQH, &rcba->d26ir);
+       writew(PIRQA, &rcba->d23ir);
+       writew(PIRQB, &rcba->d24ir);
+       writew(PIRQC, &rcba->d25ir);
+       writew(PIRQD, &rcba->d26ir);
 }
 
 int arch_misc_init(void)
 {
-       pirq_init();
-
-       return 0;
+       return pirq_init();
 }