/dts-v1/;
+#include <dt-bindings/gpio/x86-gpio.h>
+
/include/ "skeleton.dtsi"
/include/ "keyboard.dtsi"
/include/ "serial.dtsi"
/include/ "rtc.dtsi"
/include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
/ {
model = "Google Link";
intel,duplicate-por;
};
+ pch_pinctrl {
+ compatible = "intel,x86-pinctrl";
+ u-boot,dm-pre-reloc;
+ reg = <0 0>;
+
+ gpio_a0 {
+ gpio-offset = <0 0>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a1 {
+ gpio-offset = <0>;
+ mode-gpio;
+ direction = <PIN_OUTPUT>;
+ output-value = <1>;
+ };
+
+ gpio_a3 {
+ gpio-offset = <0 3>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a5 {
+ gpio-offset = <0 5>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a6 {
+ gpio-offset = <0 6>;
+ mode-gpio;
+ direction = <PIN_OUTPUT>;
+ output-value = <1>;
+ };
+
+ gpio_a7 {
+ gpio-offset = <0 7>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ };
+
+ gpio_a8 {
+ gpio-offset = <0 8>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ };
+
+ gpio_a9 {
+ gpio-offset = <0 9>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a10 {
+ u-boot,dm-pre-reloc;
+ gpio-offset = <0 10>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a11 {
+ gpio-offset = <0 11>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a12 {
+ gpio-offset = <0 12>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ };
+
+ gpio_a14 {
+ gpio-offset = <0 14>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ };
+
+ gpio_a15 {
+ gpio-offset = <0 15>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ invert;
+ };
+
+ gpio_a21 {
+ gpio-offset = <0 21>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_a24 {
+ gpio-offset = <0 24>;
+ mode-gpio;
+ output-value = <0>;
+ direction = <PIN_OUTPUT>;
+ };
+
+ gpio_a28 {
+ gpio-offset = <0 28>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_b4 {
+ gpio-offset = <0x30 4>;
+ mode-gpio;
+ direction = <PIN_OUTPUT>;
+ output-value = <1>;
+ };
+
+ gpio_b9 {
+ u-boot,dm-pre-reloc;
+ gpio-offset = <0x30 9>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_b10 {
+ u-boot,dm-pre-reloc;
+ gpio-offset = <0x30 10>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_b11 {
+ u-boot,dm-pre-reloc;
+ gpio-offset = <0x30 11>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_b25 {
+ gpio-offset = <0x30 25>;
+ mode-gpio;
+ direction = <PIN_INPUT>;
+ };
+
+ gpio_b28 {
+ gpio-offset = <0x30 28>;
+ mode-gpio;
+ direction = <PIN_OUTPUT>;
+ output-value = <1>;
+ };
+
+ };
+
pci {
compatible = "pci-x86";
#address-cells = <3>;
northbridge@0,0 {
reg = <0x00000000 0 0 0 0>;
- compatible = "intel,bd82x6x-northbridge";
u-boot,dm-pre-reloc;
+ compatible = "intel,bd82x6x-northbridge";
+ board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
+ <&gpio_b 11 0>, <&gpio_a 10 0>;
spd {
- compatible = "memory-spd";
+ u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
elpida_4Gb_1600_x16 {
+ u-boot,dm-pre-reloc;
reg = <0>;
data = [92 10 0b 03 04 19 02 02
03 52 01 08 0a 00 fe 00
00 00 00 00 00 00 00 00];
};
samsung_4Gb_1600_1.35v_x16 {
+ u-boot,dm-pre-reloc;
reg = <1>;
data = [92 11 0b 03 04 19 02 02
03 11 01 08 0a 00 fe 00
#address-cells = <1>;
#size-cells = <0>;
compatible = "intel,ich9-spi";
+ u-boot,dm-pre-reloc;
spi-flash@0 {
#size-cells = <1>;
#address-cells = <1>;
+ u-boot,dm-pre-reloc;
reg = <0>;
compatible = "winbond,w25q64",
"spi-flash";
rw-mrc-cache {
label = "rw-mrc-cache";
reg = <0x003e0000 0x00010000>;
+ u-boot,dm-pre-reloc;
};
};
};
};
microcode {
+ u-boot,dm-pre-reloc;
update@0 {
+ u-boot,dm-pre-reloc;
#include "microcode/m12306a9_0000001b.dtsi"
};
};