x86: chromebook_link: Remove dm-pre-reloc property in the cpu nodes

[u-boot] / arch / x86 / dts / chromebook_link.dts

diff --git a/arch/x86/dts/chromebook_link.dts b/arch/x86/dts/chromebook_link.dts
index fb1b31dc5e709fba60ed64a40127027e81ec5ab4..26b9f85a5dae6a4c2e80d1bb1f8891df969b3f94 100644 (file)
--- a/arch/x86/dts/chromebook_link.dts
+++ b/arch/x86/dts/chromebook_link.dts
@@ -7,6 +7,7 @@
 /include/ "serial.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
 
 / {
        model = "Google Link";
@@ -228,14 +229,16 @@
 
                northbridge@0,0 {
                        reg = <0x00000000 0 0 0 0>;
+                       u-boot,dm-pre-reloc;
                        compatible = "intel,bd82x6x-northbridge";
                        board-id-gpios = <&gpio_b 9 0>, <&gpio_b 10 0>,
                                        <&gpio_b 11 0>, <&gpio_a 10 0>;
-                       u-boot,dm-pre-reloc;
                        spd {
+                               u-boot,dm-pre-reloc;
                                #address-cells = <1>;
                                #size-cells = <0>;
                                elpida_4Gb_1600_x16 {
+                                       u-boot,dm-pre-reloc;
                                        reg = <0>;
                                        data = [92 10 0b 03 04 19 02 02
                                                03 52 01 08 0a 00 fe 00
@@ -271,6 +274,7 @@
                                                00 00 00 00 00 00 00 00];
                                };
                                samsung_4Gb_1600_1.35v_x16 {
+                                       u-boot,dm-pre-reloc;
                                        reg = <1>;
                                        data = [92 11 0b 03 04 19 02 02
                                                03 11 01 08 0a 00 fe 00
@@ -390,9 +394,11 @@
                                #address-cells = <1>;
                                #size-cells = <0>;
                                compatible = "intel,ich9-spi";
+                               u-boot,dm-pre-reloc;
                                spi-flash@0 {
                                        #size-cells = <1>;
                                        #address-cells = <1>;
+                                       u-boot,dm-pre-reloc;
                                        reg = <0>;
                                        compatible = "winbond,w25q64",
                                                        "spi-flash";
@@ -400,6 +406,7 @@
                                        rw-mrc-cache {
                                                label = "rw-mrc-cache";
                                                reg = <0x003e0000 0x00010000>;
+                                               u-boot,dm-pre-reloc;
                                        };
                                };
                        };
@@ -477,7 +484,9 @@
        };
 
        microcode {
+               u-boot,dm-pre-reloc;
                update@0 {
+                       u-boot,dm-pre-reloc;
 #include "microcode/m12306a9_0000001b.dtsi"
                };
        };