ARM: uniphier: set DRAM_SPARSE flag for LD21 boards

[u-boot] / arch / x86 / dts / chromebox_panther.dts

diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts
index 23027016e5746a51768974a2629f06ea906ceecc..b25c9194f357b792cfd7772ec4f6178427f8622b 100644 (file)
--- a/arch/x86/dts/chromebox_panther.dts
+++ b/arch/x86/dts/chromebox_panther.dts
@@ -4,13 +4,14 @@
 /include/ "serial.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
 
 / {
        model = "Google Panther";
        compatible = "google,panther", "intel,haswell";
 
        aliases {
-               spi0 = "/spi";
+               spi0 = &spi;
        };
 
        config {
@@ -18,27 +19,6 @@
                no-keyboard;
        };
 
-       gpioa {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0 0x10>;
-               bank-name = "A";
-       };
-
-       gpiob {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0x30 0x10>;
-               bank-name = "B";
-       };
-
-       gpioc {
-               compatible = "intel,ich6-gpio";
-               u-boot,dm-pre-reloc;
-               reg = <0x40 0x10>;
-               bank-name = "C";
-       };
-
        chosen {
                stdout-path = "/serial";
        };
@@ -55,11 +35,13 @@
                pch@1f,0 {
                        reg = <0x0000f800 0 0 0 0>;
                        compatible = "intel,pch9";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
 
-                       spi {
+                       spi: spi {
                                #address-cells = <1>;
                                #size-cells = <0>;
-                               compatible = "intel,ich-spi";
+                               compatible = "intel,ich9-spi";
                                spi-flash@0 {
                                        #size-cells = <1>;
                                        #address-cells = <1>;
@@ -73,6 +55,27 @@
                                        };
                                };
                        };
+
+                       gpioa {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0 0x10>;
+                               bank-name = "A";
+                       };
+
+                       gpiob {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0x30 0x10>;
+                               bank-name = "B";
+                       };
+
+                       gpioc {
+                               compatible = "intel,ich6-gpio";
+                               u-boot,dm-pre-reloc;
+                               reg = <0x40 0x10>;
+                               bank-name = "C";
+                       };
                };
        };