Merge git://git.denx.de/u-boot-uniphier

[u-boot] / arch / x86 / dts / minnowmax.dts

diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts
index b7e3ba482a3ac64d9c0f9cebf83a756745fe4197..af64c6859ce77ccfcce20daf42745da00e577173 100644 (file)
--- a/arch/x86/dts/minnowmax.dts
+++ b/arch/x86/dts/minnowmax.dts
@@ -13,6 +13,7 @@
 /include/ "serial.dtsi"
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
+/include/ "coreboot_fb.dtsi"
 
 / {
        model = "Intel Minnowboard Max";
@@ -29,12 +30,11 @@
 
        pch_pinctrl {
                compatible = "intel,x86-pinctrl";
-               io-base = <0x4c>;
+               reg = <0 0>;
 
                /* GPIO E0 */
                soc_gpio_s5_0@0 {
                        gpio-offset = <0x80 0>;
-                       pad-offset = <0x1d0>;
                        mode-gpio;
                        output-value = <0>;
                        direction = <PIN_OUTPUT>;
@@ -43,7 +43,6 @@
                /* GPIO E1 */
                soc_gpio_s5_1@0 {
                        gpio-offset = <0x80 1>;
-                       pad-offset = <0x210>;
                        mode-gpio;
                        output-value = <0>;
                        direction = <PIN_OUTPUT>;
@@ -52,7 +51,6 @@
                /* GPIO E2 */
                soc_gpio_s5_2@0 {
                        gpio-offset = <0x80 2>;
-                       pad-offset = <0x1e0>;
                        mode-gpio;
                        output-value = <0>;
                        direction = <PIN_OUTPUT>;
@@ -60,7 +58,6 @@
 
                pin_usb_host_en0@0 {
                        gpio-offset = <0x80 8>;
-                       pad-offset = <0x260>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;
@@ -68,11 +65,25 @@
 
                pin_usb_host_en1@0 {
                        gpio-offset = <0x80 9>;
-                       pad-offset = <0x250>;
                        mode-gpio;
                        output-value = <1>;
                        direction = <PIN_OUTPUT>;
                };
+
+               /*
+                * As of today, the latest version FSP (gold4) for BayTrail
+                * misses the PAD configuration of the SD controller's Card
+                * Detect signal. The default PAD value for the CD pin sets
+                * the pin to work in GPIO mode, which causes card detect
+                * status cannot be reflected by the Present State register
+                * in the SD controller (bit 16 & bit 18 are always zero).
+                *
+                * Configure this pin to function 1 (SD controller).
+                */
+               sdmmc3_cd@0 {
+                       pad-offset = <0x3a0>;
+                       mode-func = <1>;
+               };
        };
 
        chosen {
@@ -118,6 +129,7 @@
                                compatible = "intel,irq-router";
                                intel,pirq-config = "ibase";
                                intel,ibase-offset = <0x50>;
+                               intel,actl-addr = <0>;
                                intel,pirq-link = <8 8>;
                                intel,pirq-mask = <0xdee0>;
                                intel,pirq-routing = <
@@ -201,6 +213,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0 0x20>;
                                bank-name = "A";
+                               use-lvl-write-cache;
                        };
 
                        gpiob {
@@ -208,6 +221,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x20 0x20>;
                                bank-name = "B";
+                               use-lvl-write-cache;
                        };
 
                        gpioc {
@@ -215,6 +229,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x40 0x20>;
                                bank-name = "C";
+                               use-lvl-write-cache;
                        };
 
                        gpiod {
@@ -222,6 +237,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x60 0x20>;
                                bank-name = "D";
+                               use-lvl-write-cache;
                        };
 
                        gpioe {
@@ -229,6 +245,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0x80 0x20>;
                                bank-name = "E";
+                               use-lvl-write-cache;
                        };
 
                        gpiof {
@@ -236,6 +253,7 @@
                                u-boot,dm-pre-reloc;
                                reg = <0xA0 0x20>;
                                bank-name = "F";
+                               use-lvl-write-cache;
                        };
                };
        };
@@ -246,7 +264,7 @@
                fsp,mrc-init-mmio-size = <0x800>;
                fsp,mrc-init-spd-addr1 = <0xa0>;
                fsp,mrc-init-spd-addr2 = <0xa2>;
-               fsp,emmc-boot-mode = <2>;
+               fsp,emmc-boot-mode = <1>;
                fsp,enable-sdio;
                fsp,enable-sdcard;
                fsp,enable-hsuart1;
@@ -298,10 +316,10 @@
 
        microcode {
                update@0 {
-#include "microcode/m0130673322.dtsi"
+#include "microcode/m0130673325.dtsi"
                };
                update@1 {
-#include "microcode/m0130679901.dtsi"
+#include "microcode/m0130679907.dtsi"
                };
        };