};
+struct dimm_info {
+ uint32_t dimm_size;
+ uint16_t ddr_type;
+ uint16_t ddr_frequency;
+ uint8_t rank_per_dimm;
+ uint8_t channel_num;
+ uint8_t dimm_num;
+ uint8_t bank_locator;
+ /* The 5th byte is '\0' for the end of string */
+ uint8_t serial[5];
+ /* The 19th byte is '\0' for the end of string */
+ uint8_t module_part_number[19];
+ uint16_t mod_id;
+ uint8_t mod_type;
+ uint8_t bus_width;
+} __packed;
+
+struct pei_memory_info {
+ uint8_t dimm_cnt;
+ /* Maximum num of dimm is 8 */
+ struct dimm_info dimm[8];
+} __packed;
+
struct memory_area {
uint64_t start;
uint64_t size;
uint8_t x86_mask;
uint32_t x86_device;
uint64_t tsc_base; /* Initial value returned by rdtsc() */
- uint32_t tsc_base_kclocks; /* Initial tsc as a kclocks value */
- uint32_t tsc_prev; /* For show_boot_progress() */
- uint32_t tsc_mhz; /* TSC frequency in MHz */
void *new_fdt; /* Relocated FDT */
uint32_t bist; /* Built-in self test value */
enum pei_boot_mode_t pei_boot_mode;
const struct pch_gpio_map *gpio_map; /* board GPIO map */
struct memory_info meminfo; /* Memory information */
+ struct pei_memory_info pei_meminfo; /* PEI memory information */
#ifdef CONFIG_HAVE_FSP
void *hob_list; /* FSP HOB list */
#endif