SPDX: Convert all of our single license tags to Linux Kernel style

[u-boot] / arch / x86 / include / asm / msr-index.h

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 6027d593ff1978800aa5368729324b0e81721603..9c1dbe61d5965b21b4f31629e929e4c6aed89481 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Taken from the linux kernel file of the same name
  *
  * (C) Copyright 2012
  * Graeme Russ, <graeme.russ@gmail.com>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #ifndef _ASM_X86_MSR_INDEX_H
@@ -41,6 +40,9 @@
 #define EFER_FFXSR             (1<<_EFER_FFXSR)
 
 /* Intel MSRs. Some also available on other CPUs */
+#define MSR_PIC_MSG_CONTROL            0x2e
+#define  PLATFORM_INFO_SET_TDP         (1 << 29)
+
 #define MSR_IA32_PERFCTR0              0x000000c1
 #define MSR_IA32_PERFCTR1              0x000000c2
 #define MSR_FSB_FREQ                   0x000000cd
@@ -53,10 +55,17 @@
 #define SNB_C1_AUTO_UNDEMOTE           (1UL << 27)
 #define SNB_C3_AUTO_UNDEMOTE           (1UL << 28)
 
+#define MSR_BSEL_CR_OVERCLOCK_CONTROL  0x000000cd
 #define MSR_PLATFORM_INFO              0x000000ce
+#define MSR_PMG_CST_CONFIG_CONTROL     0x000000e2
+#define SINGLE_PCTL                    (1 << 11)
+
 #define MSR_MTRRcap                    0x000000fe
 #define MSR_IA32_BBL_CR_CTL            0x00000119
 #define MSR_IA32_BBL_CR_CTL3           0x0000011e
+#define MSR_POWER_MISC                 0x00000120
+#define ENABLE_ULFM_AUTOCM_MASK                (1 << 2)
+#define ENABLE_INDP_AUTOCM_MASK                (1 << 3)
 
 #define MSR_IA32_SYSENTER_CS           0x00000174
 #define MSR_IA32_SYSENTER_ESP          0x00000175
@@ -66,13 +75,28 @@
 #define MSR_IA32_MCG_STATUS            0x0000017a
 #define MSR_IA32_MCG_CTL               0x0000017b
 
+#define MSR_FLEX_RATIO                 0x194
+#define  FLEX_RATIO_LOCK               (1 << 20)
+#define  FLEX_RATIO_EN                 (1 << 16)
+
+#define MSR_IA32_MISC_ENABLES          0x000001a0
+#define MSR_TEMPERATURE_TARGET         0x1a2
 #define MSR_OFFCORE_RSP_0              0x000001a6
 #define MSR_OFFCORE_RSP_1              0x000001a7
+#define MSR_MISC_PWR_MGMT              0x1aa
+#define  MISC_PWR_MGMT_EIST_HW_DIS     (1 << 0)
 #define MSR_NHM_TURBO_RATIO_LIMIT      0x000001ad
 #define MSR_IVT_TURBO_RATIO_LIMIT      0x000001ae
 
+#define MSR_IA32_ENERGY_PERFORMANCE_BIAS       0x1b0
+#define  ENERGY_POLICY_PERFORMANCE     0
+#define  ENERGY_POLICY_NORMAL          6
+#define  ENERGY_POLICY_POWERSAVE       15
+
 #define MSR_LBR_SELECT                 0x000001c8
 #define MSR_LBR_TOS                    0x000001c9
+#define MSR_IA32_PLATFORM_DCA_CAP      0x1f8
+#define MSR_POWER_CTL                  0x000001fc
 #define MSR_LBR_NHM_FROM               0x00000680
 #define MSR_LBR_NHM_TO                 0x000006c0
 #define MSR_LBR_CORE_FROM              0x00000040
@@ -136,9 +160,31 @@
 
 /* Run Time Average Power Limiting (RAPL) Interface */
 
-#define MSR_RAPL_POWER_UNIT            0x00000606
+#define MSR_PKG_POWER_SKU_UNIT         0x00000606
+
+#define MSR_C_STATE_LATENCY_CONTROL_0  0x60a
+#define MSR_C_STATE_LATENCY_CONTROL_1  0x60b
+#define MSR_C_STATE_LATENCY_CONTROL_2  0x60c
+#define MSR_C_STATE_LATENCY_CONTROL_3  0x633
+#define MSR_C_STATE_LATENCY_CONTROL_4  0x634
+#define MSR_C_STATE_LATENCY_CONTROL_5  0x635
+#define  IRTL_VALID                    (1 << 15)
+#define  IRTL_1_NS                     (0 << 10)
+#define  IRTL_32_NS                    (1 << 10)
+#define  IRTL_1024_NS                  (2 << 10)
+#define  IRTL_32768_NS                 (3 << 10)
+#define  IRTL_1048576_NS               (4 << 10)
+#define  IRTL_33554432_NS              (5 << 10)
+#define  IRTL_RESPONSE_MASK            (0x3ff)
 
 #define MSR_PKG_POWER_LIMIT            0x00000610
+/* long duration in low dword, short duration in high dword */
+#define  PKG_POWER_LIMIT_MASK          0x7fff
+#define  PKG_POWER_LIMIT_EN            (1 << 15)
+#define  PKG_POWER_LIMIT_CLAMP         (1 << 16)
+#define  PKG_POWER_LIMIT_TIME_SHIFT    17
+#define  PKG_POWER_LIMIT_TIME_MASK     0x7f
+
 #define MSR_PKG_ENERGY_STATUS          0x00000611
 #define MSR_PKG_PERF_STATUS            0x00000613
 #define MSR_PKG_POWER_INFO             0x00000614
@@ -156,8 +202,19 @@
 #define MSR_PP1_POWER_LIMIT            0x00000640
 #define MSR_PP1_ENERGY_STATUS          0x00000641
 #define MSR_PP1_POLICY                 0x00000642
-
+#define MSR_CONFIG_TDP_NOMINAL         0x00000648
+#define MSR_TURBO_ACTIVATION_RATIO     0x0000064c
 #define MSR_CORE_C1_RES                        0x00000660
+#define MSR_IACORE_RATIOS              0x0000066a
+#define MSR_IACORE_TURBO_RATIOS                0x0000066c
+#define MSR_IACORE_VIDS                        0x0000066b
+#define MSR_IACORE_TURBO_VIDS          0x0000066d
+#define MSR_PKG_TURBO_CFG1             0x00000670
+#define MSR_CPU_TURBO_WKLD_CFG1                0x00000671
+#define MSR_CPU_TURBO_WKLD_CFG2                0x00000672
+#define MSR_CPU_THERM_CFG1             0x00000673
+#define MSR_CPU_THERM_CFG2             0x00000674
+#define MSR_CPU_THERM_SENS_CFG         0x00000675
 
 #define MSR_AMD64_MC0_MASK             0xc0010044
 
@@ -326,6 +383,8 @@
 #define MSR_AMD_PERF_STATUS            0xc0010063
 #define MSR_AMD_PERF_CTL               0xc0010062
 
+#define MSR_PMG_CST_CONFIG_CTL         0x000000e2
+#define MSR_PMG_IO_CAPTURE_ADR         0x000000e4
 #define MSR_IA32_MPERF                 0x000000e7
 #define MSR_IA32_APERF                 0x000000e8
 
@@ -346,6 +405,7 @@
 #define MSR_THERM2_CTL_TM_SELECT       (1ULL << 16)
 
 #define MSR_IA32_MISC_ENABLE           0x000001a0
+#define H_MISC_DISABLE_TURBO           (1 << 6)
 
 #define MSR_IA32_TEMPERATURE_TARGET    0x000001a2