style fixes

[cc65] / asminc / pce.inc

diff --git a/asminc/pce.inc b/asminc/pce.inc
index 4680ba826f8762ac90872c61cd135330ef78837e..2d2843143e1c8c31ca2658981c68946cc90e8eb5 100644 (file)
--- a/asminc/pce.inc
+++ b/asminc/pce.inc
@@ -2,44 +2,44 @@
 ; PCE definitions. By Groepaz/Hitmem.
 ;
 
-;; FIXME: optimize zeropage usage
-
-CURS_X      = $30
-CURS_Y      = $31
-SCREEN_PTR  = $32       ;2
-CRAM_PTR    = $34       ;2
-CHARCOLOR   = $36
-RVS         = $37
-BGCOLOR     = $38
-tickcount   = $39       ;4
-
-screenrows = (224/8)
-charsperline = 61
-
-CH_HLINE = 1
-CH_VLINE = 2
+; FIXME: optimize zeropage usage
+CURS_X          = $30
+CURS_Y          = $31
+SCREEN_PTR      = $32           ;2
+CRAM_PTR        = $34           ;2
+CHARCOLOR       = $36
+RVS             = $37
+BGCOLOR         = $38
+tickcount       = $39           ;4
+
+; FIXME: screen dimensions my change according to selected video mode
+screenrows      = (224/8)
+charsperline    = 61
+
+CH_HLINE        = 1
+CH_VLINE        = 2
 
 ; huc6270 - Video Display Controller (vdc)
 
-VDC_MAWR = 0 ; Memory Address Write Register
-VDC_MARR = 1 ; Memory Address Read Register
-VDC_VWR  = 2 ; VRAM Write Register
-VDC_VRR  = 3 ; VRAM Read Register
-VDC_CR   = 4 ; Control Register
-VDC_RCR  = 5 ; Raster Counter Register
-VDC_BXR  = 6 ; Background X-Scroll Register
-VDC_BYR  = 7 ; Background Y-Scroll Register
-VDC_MWR  = 8 ; Memory-access Width Register
-VDC_HSR  = 9 ; Horizontal Sync Register (?)
-VDC_HDR  =10 ; Horizontal Display Register (?)
-VDC_VPR  =11 ; (unknown)
-VDC_VDW  =12 ; (unknown use)
-VDC_VCR  =13 ; (unknown use)
-VDC_DCR  =14 ; (DMA) Control Register
-VDC_SOUR =15 ; (DMA) Source Register
-VDC_DESR =16 ; (DMA) Destination Register
-VDC_LENR =17 ; (DMA) Length Register
-VDC_SATB =18 ; Sprite Attribute Table
+VDC_MAWR        = 0             ; Memory Address Write Register
+VDC_MARR        = 1             ; Memory Address Read Register
+VDC_VWR         = 2             ; VRAM Write Register
+VDC_VRR         = 3             ; VRAM Read Register
+VDC_CR          = 4             ; Control Register
+VDC_RCR         = 5             ; Raster Counter Register
+VDC_BXR         = 6             ; Background X-Scroll Register
+VDC_BYR         = 7             ; Background Y-Scroll Register
+VDC_MWR         = 8             ; Memory-access Width Register
+VDC_HSR         = 9             ; Horizontal Sync Register (?)
+VDC_HDR         = 10            ; Horizontal Display Register (?)
+VDC_VPR         = 11            ; (unknown)
+VDC_VDW         = 12            ; (unknown use)
+VDC_VCR         = 13            ; (unknown use)
+VDC_DCR         = 14            ; (DMA) Control Register
+VDC_SOUR        = 15            ; (DMA) Source Register
+VDC_DESR        = 16            ; (DMA) Destination Register
+VDC_LENR        = 17            ; (DMA) Length Register
+VDC_SATB        = 18            ; Sprite Attribute Table
 
 ; VDC port
 ; Note: absolute addressing mode must be used when writing to this port
@@ -54,21 +54,21 @@ VDC_DATA_HI     = $0003
 ; bitmap of the palette data is this: 0000000gggrrrbbb.
 ; You can read and write the DAC-registers.
 
-VCE         = $0400 ; base
+VCE             = $0400         ; base
 
-VCE_CTRL    = $0400 ; write$00 to reset
-VCE_ADDR_LO = $0402 ; LSB of byte offset into palette
-VCE_ADDR_HI = $0403 ; MSB of byte offset into palette
-VCE_DATA_LO = $0404 ; LSB of 16-bit palette data
-VCE_DATA_HI = $0405 ; MSB of 16-bit palette data
+VCE_CTRL        = $0400         ; write$00 to reset
+VCE_ADDR_LO     = $0402         ; LSB of byte offset into palette
+VCE_ADDR_HI     = $0403         ; MSB of byte offset into palette
+VCE_DATA_LO     = $0404         ; LSB of 16-bit palette data
+VCE_DATA_HI     = $0405         ; MSB of 16-bit palette data
 
 ; programmable sound generator (PSG)
 
-PSG             = $0800 ; base
+PSG             = $0800         ; base
 
 ; timer
 
-TIMER           = $0c00 ; base
+TIMER           = $0c00         ; base
 
 TIMER_COUNT     = $0c00
 TIMER_CTRL      = $0c01