; PCE definitions. By Groepaz/Hitmem.
;
-;; FIXME: optimize zeropage usage
-
-CURS_X = $30
-CURS_Y = $31
-SCREEN_PTR = $32 ;2
-CRAM_PTR = $34 ;2
-CHARCOLOR = $36
-RVS = $37
-BGCOLOR = $38
-_tickcount = $39 ;2
-
-screenrows = (224/8)
-charsperline = (512/8)
-xsize = charsperline
-
-CH_HLINE = 7
-CH_VLINE = 7
-
-; huc6270 - Video Display Controller (vdc)
-
-VDC_MAWR = 0 ; Memory Address Write Register
-VDC_MARR = 1 ; Memory Address Read Register
-VDC_VWR = 2 ; VRAM Write Register
-VDC_VRR = 3 ; VRAM Read Register
-VDC_CR = 4 ; Control Register
-VDC_RCR = 5 ; Raster Counter Register
-VDC_BXR = 6 ; Background X-Scroll Register
-VDC_BYR = 7 ; Background Y-Scroll Register
-VDC_MWR = 8 ; Memory-access Width Register
-VDC_HSR = 9 ; Horizontal Sync Register (?)
-VDC_HDR =10 ; Horizontal Display Register (?)
-VDC_VPR =11 ; (unknown)
-VDC_VDW =12 ; (unknown use)
-VDC_VCR =13 ; (unknown use)
-VDC_DCR =14 ; (DMA) Control Register
-VDC_SOUR =15 ; (DMA) Source Register
-VDC_DESR =16 ; (DMA) Destination Register
-VDC_LENR =17 ; (DMA) Length Register
-VDC_SATB =18 ; Sprite Attribute Table
+; FIXME: screen dimensions my change according to selected video mode
+screenrows = (224/8)
+charsperline = 61
+
+CH_HLINE = 1
+CH_VLINE = 2
+
+; huc6270 - Video Display Controller (VDC)
+
+VDC_MAWR = 0 ; Memory Address Write Register
+VDC_MARR = 1 ; Memory Address Read Register
+VDC_VWR = 2 ; VRAM Write Register (write only)
+VDC_VRR = 2 ; VRAM Read Register (read only)
+VDC_UNK03 = 3 ; (unknown)
+VDC_UNK04 = 4 ; (unknown)
+VDC_CR = 5 ; Control Register
+VDC_RCR = 6 ; Raster Counter Register
+VDC_BXR = 7 ; Background X-Scroll Register
+VDC_BYR = 8 ; Background Y-Scroll Register
+VDC_MWR = 9 ; Memory-access Width Register
+VDC_HSR = 10 ; Horizontal Sync Register
+VDC_HDR = 11 ; Horizontal Display Register
+VDC_VPR = 12 ; Vertical synchronous register
+VDC_VDW = 13 ; Vertical display register
+VDC_VCR = 14 ; Vertical display END position register
+VDC_DCR = 15 ; (DMA) Control Register
+VDC_SOUR = 16 ; (DMA) Source Register
+VDC_DESR = 17 ; (DMA) Destination Register
+VDC_LENR = 18 ; (DMA) Length Register
+VDC_SATB = 19 ; Sprite Attribute Table
+
+; VDC port
+; Note: absolute addressing mode must be used when writing to this port
VDC_CTRL = $0000
VDC_DATA_LO = $0002
; bitmap of the palette data is this: 0000000gggrrrbbb.
; You can read and write the DAC-registers.
-VCE_CTRL = $0400 ; write$00 to reset
-VCE_ADDR_LO = $0402 ; LSB of byte offset into palette
-VCE_ADDR_HI = $0403 ; MSB of byte offset into palette
-VCE_DATA_LO = $0404 ; LSB of 16-bit palette data
-VCE_DATA_HI = $0405 ; MSB of 16-bit palette data
+VCE = $0400 ; base
+
+VCE_CTRL = $0400 ; write$00 to reset
+VCE_ADDR_LO = $0402 ; LSB of byte offset into palette
+VCE_ADDR_HI = $0403 ; MSB of byte offset into palette
+VCE_DATA_LO = $0404 ; LSB of 16-bit palette data
+VCE_DATA_HI = $0405 ; MSB of 16-bit palette data
+
+; programmable sound generator (PSG)
+
+PSG = $0800 ; base
+
+PSG_CHAN_SELECT = $0800
+PSG_GLOBAL_PAN = $0801
+PSG_FREQ_LO = $0802
+PSG_FREQ_HI = $0803
+PSG_CHAN_CTRL = $0804
+PSG_CHAN_PAN = $0805
+PSG_CHAN_DATA = $0806
+PSG_NOISE = $0807
+PSG_LFO_FREQ = $0808
+PSG_LFO_CTRL = $0809
+
+; timer
+
+TIMER = $0c00 ; base
TIMER_COUNT = $0c00
TIMER_CTRL = $0c01
CDR_MEM_DISABLE = $1803
CDR_MEM_ENABLE = $1807
-;; lda abs
-.macro ldaio arg1
- .byte $ad
- .word arg1
-.endmacro
-;; sta abs
-.macro staio arg1
- .byte $8d
- .word arg1
-.endmacro
-;; stz abs
-.macro stzio arg1
- .byte $9c
- .word arg1
-.endmacro
-
; Write VDC register
.macro VREG arg1,arg2
st0 #arg1