ARM: mvebu: a38x: sync ddr training code with upstream

[u-boot] / board / Marvell / db-88f6820-gp / db-88f6820-gp.c

diff --git a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
index e661fa129671d3ef1cdd9d4dd65abfb604d3f566..ee12ca68ec2a1f5ed1ec7895d27bd823d3760cdc 100644 (file)
--- a/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
+++ b/board/Marvell/db-88f6820-gp/db-88f6820-gp.c
@@ -1,22 +1,21 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2015 Stefan Roese <sr@denx.de>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
 #include <i2c.h>
 #include <miiphy.h>
+#include <netdev.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
 #include <asm/arch/soc.h>
 
-#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
+#include "../drivers/ddr/marvell/a38x/ddr3_init.h"
+#include <../serdes/a38x/high_speed_env_spec.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define BIT(nr)                                (1UL << (nr))
-
 #define ETH_PHY_CTRL_REG               0
 #define ETH_PHY_CTRL_POWER_DOWN_BIT    11
 #define ETH_PHY_CTRL_POWER_DOWN_MASK   (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
@@ -56,12 +55,29 @@ static struct marvell_io_exp io_exp[] = {
        { 0x21, 3, 0xC0 }  /* Output Data, register#1 */
 };
 
+static struct serdes_map board_serdes_map[] = {
+       {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0},
+       {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
+       {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}
+};
+
+int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
+{
+       *serdes_map_array = board_serdes_map;
+       *count = ARRAY_SIZE(board_serdes_map);
+       return 0;
+}
+
 /*
  * Define the DDR layout / topology here in the board file. This will
  * be used by the DDR3 init code in the SPL U-Boot version to configure
  * the DDR3 controller.
  */
-static struct hws_topology_map board_topology_map = {
+static struct mv_ddr_topology_map board_topology_map = {
+       DEBUG_LEVEL_ERROR,
        0x1, /* active interfaces */
        /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
        { { { {0x1, 0, 0, 0},
@@ -70,16 +86,18 @@ static struct hws_topology_map board_topology_map = {
              {0x1, 0, 0, 0},
              {0x1, 0, 0, 0} },
            SPEED_BIN_DDR_1866L,        /* speed_bin */
-           BUS_WIDTH_8,                /* memory_width */
-           MEM_4G,                     /* mem_size */
+           MV_DDR_DEV_WIDTH_8BIT,      /* memory_width */
+           MV_DDR_DIE_CAP_4GBIT,       /* mem_size */
            DDR_FREQ_800,               /* frequency */
-           0, 0,                       /* cas_l cas_wl */
-           HWS_TEMP_LOW} },            /* temperature */
-       5,                              /* Num Of Bus Per Interface*/
-       BUS_MASK_32BIT                  /* Busses mask */
+           0, 0,                       /* cas_wl cas_l */
+           MV_DDR_TEMP_LOW} },         /* temperature */
+       BUS_MASK_32BIT,                 /* Busses mask */
+       MV_DDR_CFG_DEFAULT,             /* ddr configuration data source */
+       { {0} },                        /* raw spd data */
+       {0}                             /* timing parameters */
 };
 
-struct hws_topology_map *ddr3_get_topology_map(void)
+struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
 {
        /* Return the board topology as defined in the board code */
        return &board_topology_map;
@@ -132,3 +150,9 @@ int checkboard(void)
 
        return 0;
 }
+
+int board_eth_init(bd_t *bis)
+{
+       cpu_eth_init(bis); /* Built in controller(s) come first */
+       return pci_eth_init(bis);
+}