Merge branch 'master' of git://git.denx.de/u-boot-arm

[u-boot] / board / Marvell / openrd / openrd.c

diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
index e53fa16a249ec748e7c78de3a6d4a5521b5bbf0b..2a10e69fafd86591acdd6e4dd3c6e8ca85f011d8 100644 (file)
--- a/board/Marvell/openrd/openrd.c
+++ b/board/Marvell/openrd/openrd.c
@@ -29,6 +29,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "openrd.h"
@@ -110,7 +111,13 @@ int board_init(void)
        /*
         * arch number of board
         */
+#if defined(CONFIG_BOARD_IS_OPENRD_BASE)
        gd->bd->bi_arch_number = MACH_TYPE_OPENRD_BASE;
+#elif defined(CONFIG_BOARD_IS_OPENRD_CLIENT)
+       gd->bd->bi_arch_number = MACH_TYPE_OPENRD_CLIENT;
+#elif defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+       gd->bd->bi_arch_number = MACH_TYPE_OPENRD_ULTIMATE;
+#endif
 
        /* adress of boot parameters */
        gd->bd->bi_boot_params = kw_sdram_bar(0) + 0x100;
@@ -118,12 +125,11 @@ int board_init(void)
 }
 
 #ifdef CONFIG_RESET_PHY_R
-/* Configure and enable MV88E1116 PHY */
-void reset_phy(void)
+/* Configure and enable MV88E1116/88E1121 PHY */
+void mv_phy_init(char *name)
 {
        u16 reg;
        u16 devadr;
-       char *name = "egiga0";
 
        if (miiphy_set_current_dev(name))
                return;
@@ -148,6 +154,24 @@ void reset_phy(void)
        /* reset the phy */
        miiphy_reset(name, devadr);
 
-       printf("88E1116 Initialized on %s\n", name);
+       printf(PHY_NO" Initialized on %s\n", name);
+}
+
+void reset_phy(void)
+{
+       mv_phy_init("egiga0");
+
+#ifdef CONFIG_BOARD_IS_OPENRD_CLIENT
+       /* Kirkwood ethernet driver is written with the assumption that in case
+        * of multiple PHYs, their addresses are consecutive. But unfortunately
+        * in case of OpenRD-Client, PHY addresses are not consecutive.*/
+       miiphy_write("egiga1", 0xEE, 0xEE, 24);
+#endif
+
+#if defined(CONFIG_BOARD_IS_OPENRD_CLIENT) || \
+       defined(CONFIG_BOARD_IS_OPENRD_ULTIMATE)
+       /* configure and initialize both PHY's */
+       mv_phy_init("egiga1");
+#endif
 }
 #endif /* CONFIG_RESET_PHY_R */