ppc4xx: Cleanup for partial linking and --gc-sections

[u-boot] / board / amcc / canyonlands / canyonlands.c

diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 23874d2667dc6510a71d1a7dd84c5ceda10d8d38..80e2739fe011218e7c09fda94e617c3cdf7971b0 100644 (file)
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -19,7 +19,7 @@
  */
 
 #include <common.h>
-#include <ppc440.h>
+#include <asm/ppc440.h>
 #include <libfdt.h>
 #include <fdt_support.h>
 #include <i2c.h>
@@ -27,14 +27,24 @@
 #include <asm/io.h>
 #include <asm/mmu.h>
 #include <asm/4xx_pcie.h>
-#include <asm/gpio.h>
+#include <asm/ppc4xx-gpio.h>
 #include <asm/errno.h>
 
 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CONFIG_SYS_BCSR3_PCIE          0x10
+struct board_bcsr {
+       u8      board_id;
+       u8      cpld_rev;
+       u8      led_user;
+       u8      board_status;
+       u8      reset_ctrl;
+       u8      flash_ctrl;
+       u8      eth_ctrl;
+       u8      usb_ctrl;
+       u8      irq_ctrl;
+};
 
 #define BOARD_CANYONLANDS_PCIE 1
 #define BOARD_CANYONLANDS_SATA 2
@@ -112,6 +122,9 @@ int board_early_init_f(void)
 {
 #if !defined(CONFIG_ARCHES)
        u32 sdr0_cust0;
+       struct board_bcsr *bcsr_data =
+               (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+
 #endif
 
        /*
@@ -172,35 +185,69 @@ int board_early_init_f(void)
 
 #if !defined(CONFIG_ARCHES)
        /* Enable ethernet and take out of reset */
-       out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
+       out_8(&bcsr_data->eth_ctrl, 0) ;
 
        /* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
-       out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
-
-       /* Enable USB host & USB-OTG */
-       out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
-
+       out_8(&bcsr_data->flash_ctrl, 0) ;
        mtsdr(SDR0_SRST1, 0);   /* Pull AHB out of reset default=1 */
 
        /* Setup PLB4-AHB bridge based on the system address map */
        mtdcr(AHB_TOP, 0x8000004B);
        mtdcr(AHB_BOT, 0x8000004B);
 
-       if (pvr_460ex()) {
-               /*
-                * Configure USB-STP pins as alternate and not GPIO
-                * It seems to be neccessary to configure the STP pins as GPIO
-                * input at powerup (perhaps while USB reset is asserted). So
-                * we configure those pins to their "real" function now.
-                */
-               gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-               gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
-       }
 #endif
 
        return 0;
 }
 
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
+int usb_board_init(void)
+{
+       struct board_bcsr *bcsr_data =
+               (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+       u8 val;
+
+       /* Enable USB host & USB-OTG */
+       val = in_8(&bcsr_data->usb_ctrl);
+       val &= ~(BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+       out_8(&bcsr_data->usb_ctrl, val);
+
+       /*
+        * Configure USB-STP pins as alternate and not GPIO
+        * It seems to be neccessary to configure the STP pins as GPIO
+        * input at powerup (perhaps while USB reset is asserted). So
+        * we configure those pins to their "real" function now.
+        */
+       gpio_config(16, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+       gpio_config(19, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1);
+
+       return 0;
+}
+
+int usb_board_stop(void)
+{
+       struct board_bcsr *bcsr_data =
+               (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
+       u8 val;
+
+       /* Disable USB host & USB-OTG */
+       val = in_8(&bcsr_data->usb_ctrl);
+       val |= (BCSR_USBCTRL_OTG_RST | BCSR_USBCTRL_HOST_RST);
+       out_8(&bcsr_data->usb_ctrl, val);
+
+       /* Reconfigure USB-STP pins as input */
+       gpio_config(16, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+       gpio_config(19, GPIO_IN , GPIO_SEL, GPIO_OUT_0);
+
+       return 0;
+}
+
+int usb_board_init_fail(void)
+{
+       return usb_board_stop();
+}
+#endif /* CONFIG_USB_OHCI_NEW && CONFIG_SYS_USB_OHCI_BOARD_INIT */
+
 #if !defined(CONFIG_ARCHES)
 static void canyonlands_sata_init(int board_type)
 {
@@ -244,11 +291,13 @@ int get_cpu_num(void)
 #if !defined(CONFIG_ARCHES)
 int checkboard(void)
 {
+       struct board_bcsr *bcsr_data =
+               (struct board_bcsr *)CONFIG_SYS_BCSR_BASE;
        char *s = getenv("serial#");
 
        if (pvr_460ex()) {
                printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
-               if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
+               if (in_8(&bcsr_data->board_status) & BCSR_SELECT_PCIE)
                        gd->board_type = BOARD_CANYONLANDS_PCIE;
                else
                        gd->board_type = BOARD_CANYONLANDS_SATA;
@@ -268,7 +317,7 @@ int checkboard(void)
                break;
        }
 
-       printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
+       printf(", Rev. %X", in_8(&bcsr_data->cpld_rev));
 
        if (s != NULL) {
                puts(", serial# ");
@@ -314,18 +363,6 @@ int checkboard(void)
 }
 #endif /* !defined(CONFIG_ARCHES) */
 
-#if defined(CONFIG_NAND_U_BOOT)
-/*
- * NAND booting U-Boot version uses a fixed initialization, since the whole
- * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
- * code.
- */
-phys_size_t initdram(int board_type)
-{
-       return CONFIG_SYS_MBYTES_SDRAM << 20;
-}
-#endif
-
 #if defined(CONFIG_PCI)
 int board_pcie_first(void)
 {