Merge branch 'u-boot-imx/master' into 'u-boot-arm/master'

[u-boot] / board / amcc / canyonlands / init.S

diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 680feaa6a9671707422be623ea0654b79d4a77ff..bf00bd6bcaa186e802158363b861e9fe70d9a012 100644 (file)
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -2,23 +2,7 @@
  * (C) Copyright 2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.         See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -47,13 +31,7 @@ tlbtab:
         * use the speed up boot process. It is patched after relocation to
         * enable SA_I
         */
-#ifndef CONFIG_NAND_SPL
        tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_RWX | SA_G) /* TLB 0 */
-#else
-       tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_RWX | SA_G)
-       tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_RWX | SA_IG)
-       tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_RWX | SA_IG)
-#endif
 
        /*
         * TLB entries for SDRAM are not needed on this platform.
@@ -80,7 +58,7 @@ tlbtab:
 
 #if !defined(CONFIG_ARCHES)
        /* TLB-entry for NAND */
-       tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
+       tlbentry(CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 4, AC_RWX | SA_IG)
 
        /* TLB-entry for CPLD */
        tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_RW | SA_IG)
@@ -111,31 +89,3 @@ tlbtab:
 #endif
 
        tlbtab_end
-
-#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
-       /*
-        * For NAND booting the first TLB has to be reconfigured to full size
-        * and with caching disabled after running from RAM!
-        */
-#define TLB00  TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01  TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
-#define TLB02  TLB2(AC_RWX | SA_IG)
-
-       .globl  reconfig_tlb0
-reconfig_tlb0:
-       sync
-       isync
-       addi    r4,r0,0x0000            /* TLB entry #0 */
-       lis     r5,TLB00@h
-       ori     r5,r5,TLB00@l
-       tlbwe   r5,r4,0x0000            /* Save it out */
-       lis     r5,TLB01@h
-       ori     r5,r5,TLB01@l
-       tlbwe   r5,r4,0x0001            /* Save it out */
-       lis     r5,TLB02@h
-       ori     r5,r5,TLB02@l
-       tlbwe   r5,r4,0x0002            /* Save it out */
-       sync
-       isync
-       blr
-#endif