Merge branch 'lwmon5' of /home/wd/git/u-boot/projects

[u-boot] / board / amcc / kilauea / init.S

diff --git a/board/amcc/kilauea/init.S b/board/amcc/kilauea/init.S
index 96358c66514a7c3c6c068a4f6cf1847204abbf3e..8cd534cd6b9aec9b301ad56cdf4e5734f0e97a3c 100644 (file)
--- a/board/amcc/kilauea/init.S
+++ b/board/amcc/kilauea/init.S
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2007
+ * (C) Copyright 2007-2008
  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
  * Based on code provided from UDTech and AMCC
@@ -29,15 +29,16 @@
 #include <ppc_asm.tmpl>
 #include <ppc_defs.h>
 
-#define mtsdram_as(reg, value)         \
-       addi    r4,0,reg        ;       \
+#define mtsdram_as(reg, value)         \
+       addi    r4,0,reg        ;       \
        mtdcr   memcfga,r4      ;       \
-       addis   r4,0,value@h    ;       \
+       addis   r4,0,value@h    ;       \
        ori     r4,r4,value@l   ;       \
        mtdcr   memcfgd,r4      ;
 
        .globl  ext_bus_cntlr_init
 ext_bus_cntlr_init:
+#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
 
        /*
         * DDR2 setup
@@ -63,7 +64,7 @@ ext_bus_cntlr_init:
        /* SET SDRAM_MB3CF  - Not enabled */
        mtsdram_as(SDRAM_MB3CF, 0x00000000);
 
-       /* SDRAM_CLKTR: Adv Addr clock by 90 deg */
+       /* SDRAM_CLKTR: Adv Addr clock by 180 deg */
        mtsdram_as(SDRAM_CLKTR, 0x80000000);
 
        /* Refresh Time register (0x30) Refresh every 7.8125uS */
@@ -148,5 +149,6 @@ pll_wait:
 
        /* Enable memory controller */
        mtsdram_as(SDRAM_MCOPT2, 0x28000000);
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
 
        blr