* (C) Copyright 2007
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
-#include <ppc4xx.h>
-#include <ppc405.h>
+#include <asm/ppc4xx.h>
+#include <asm/ppc405.h>
#include <libfdt.h>
+#include <fdt_support.h>
#include <asm/processor.h>
-#include <asm-ppc/io.h>
+#include <asm/io.h>
+#include <asm/errno.h>
#if defined(CONFIG_PCI)
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
-void fpga_init(void)
+static int board_cpld_version(void)
{
+ u32 cpld;
+
+ cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE);
+ if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) {
+ /*
+ * Magic not found -> "old" CPLD revision which needs
+ * the "old" EBC configuration
+ */
+ mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) |
+ EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE |
+ EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) |
+ EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) |
+ EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) |
+ EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED |
+ EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED);
+
+ /*
+ * Return 0 for "old" CPLD version
+ */
+ return 0;
+ }
+
/*
- * Set FPGA regs
+ * Magic found -> "new" CPLD revision which needs no new
+ * EBC configuration
*/
- out32(CFG_FPGA_BASE, 0xff570cc0);
+ return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8;
}
/*
| interrupts again.
+-------------------------------------------------------------------*/
- mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic2er, 0x00000000); /* disable all interrupts */
- mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic2pr, 0xf7ffffff); /* Set Interrupt Polarities */
- mtdcr (uic2tr, 0x01e1fff8); /* Set Interrupt Trigger Levels */
- mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic2sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic1er, 0x00000000); /* disable all interrupts */
- mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic1pr, 0xfffac785); /* Set Interrupt Polarities */
- mtdcr (uic1tr, 0x001d0040); /* Set Interrupt Trigger Levels */
- mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic1sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic1sr, 0xffffffff); /* clear all interrupts */
-
- mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */
- mtdcr (uic0er, 0x0000000a); /* Disable all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */
+ mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */
+ mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */
+ mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */
+
+ mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */
+ mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */
/* Except cascade UIC0 and UIC1 */
- mtdcr (uic0cr, 0x00000000); /* Set Critical / Non Critical interrupts */
- mtdcr (uic0pr, 0xffbfefef); /* Set Interrupt Polarities */
- mtdcr (uic0tr, 0x00007000); /* Set Interrupt Trigger Levels */
- mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
- mtdcr (uic0sr, 0x00000000); /* clear all interrupts */
- mtdcr (uic0sr, 0xffffffff); /* clear all interrupts */
+ mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */
+ mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */
+ mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */
+ mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */
+ mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */
+ mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */
/*
* Note: Some cores are still in reset when the chip starts, so
*/
mtsdr(SDR0_SRST, 0);
- fpga_init();
-
/* Configure 405EX for NAND usage */
val = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NRB_BUSY |
- (0x80000000 >> (28 + CFG_NAND_CS));
+ (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
mtsdr(SDR0_CUST0, val);
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ /*
+ * The CPLD version detection has to be the first access to
+ * the CPLD, so we need to make this access this early and
+ * save the CPLD version for later.
+ */
+ gd->board_type = board_cpld_version();
+
+ /*
+ * Configure FPGA register with PCIe reset
+ */
+ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
+ mdelay(50);
+ out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
+
return 0;
}
int misc_init_r(void)
{
-#ifdef CFG_ENV_IS_IN_FLASH
+#ifdef CONFIG_ENV_IS_IN_FLASH
/* Monitor protection ON by default */
flash_protect(FLAG_PROTECT_SET,
- -CFG_MONITOR_LEN,
+ -CONFIG_SYS_MONITOR_LEN,
0xffffffff,
&flash_info[0]);
#endif
return 0;
}
-int checkboard (void)
+static int is_405exr(void)
{
- char *s = getenv("serial#");
+ u32 pvr = get_pvr();
- printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
+ if (pvr & 0x00000004)
+ return 0; /* bit 2 set -> 405EX */
- if (s != NULL) {
- puts(", serial# ");
- puts(s);
- }
- putc('\n');
-
- return (0);
+ return 1; /* bit 2 cleared -> 405EXr */
}
-/*************************************************************************
- * pci_pre_init
- *
- * This routine is called just prior to registering the hose and gives
- * the board the opportunity to check things. Returning a value of zero
- * indicates that things are bad & PCI initialization should be aborted.
- *
- * Different boards may wish to customize the pci controller structure
- * (add regions, override default access routines, etc) or perform
- * certain pre-initialization actions.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI)
-int pci_pre_init(struct pci_controller * hose )
+int board_emac_count(void)
{
- return 0;
-}
-#endif /* defined(CONFIG_PCI) */
-
-/*************************************************************************
- * pci_target_init
- *
- * The bootstrap configuration provides default settings for the pci
- * inbound map (PIM). But the bootstrap config choices are limited and
- * may not be sufficient for a given board.
- *
- ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
-void pci_target_init(struct pci_controller * hose )
-{
- /*-------------------------------------------------------------------+
- * Disable everything
- *-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0SA, 0 ); /* disable */
- out32r( PCIX0_PIM1SA, 0 ); /* disable */
- out32r( PCIX0_PIM2SA, 0 ); /* disable */
- out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */
-
- /*-------------------------------------------------------------------+
- * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
- * strapping options to not support sizes such as 128/256 MB.
- *-------------------------------------------------------------------*/
- out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
- out32r( PCIX0_PIM0LAH, 0 );
- out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
-
- out32r( PCIX0_BAR0, 0 );
-
- /*-------------------------------------------------------------------+
- * Program the board's subsystem id/vendor id
- *-------------------------------------------------------------------*/
- out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
- out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
-
- out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
+ /*
+ * 405EXr only has one EMAC interface, 405EX has two
+ */
+ if (is_405exr())
+ return 1;
+ else
+ return 2;
}
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
-#ifdef CONFIG_PCI
-static int pcie_port_is_rootpoint(int port)
+/*
+ * Override the weak default implementation and return the
+ * last PCIe slot number (max number - 1).
+ */
+int board_pcie_last(void)
{
- return 1;
+ /*
+ * 405EXr only has one EMAC interface, 405EX has two
+ */
+ if (is_405exr())
+ return 1 - 1;
+ else
+ return 2 - 1;
}
-static struct pci_controller pcie_hose[2] = {{0},{0}};
-
-void pcie_setup_hoses(int busno)
+int checkboard (void)
{
- struct pci_controller *hose;
- int i, bus;
- bus = busno;
- char *env;
- unsigned int delay;
-
- for (i = 0; i < 2; i++) {
+ char buf[64];
+ int i = getenv_f("serial#", buf, sizeof(buf));
- if (pcie_port_is_rootpoint(i)) {
- printf("PORT%d will be configured as root-complex\n", i);
- if (ppc4xx_init_pcie_rootport(i)) {
- printf("PCIE%d: initialization failed\n", i);
- continue;
- }
- } else {
- printf("PORT%d will be configured as endpoint\n", i);
- if (ppc4xx_init_pcie_endport(i)) {
- printf("PCIE%d: initialization failed\n", i);
- continue;
- }
- }
+ if (is_405exr())
+ printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
+ else
+ printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
- hose = &pcie_hose[i];
- hose->first_busno = bus;
- hose->last_busno = bus;
- hose->current_busno = bus;
-
- /* setup mem resource */
- pci_set_region(hose->regions + 0,
- CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
- CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
- CFG_PCIE_MEMSIZE,
- PCI_REGION_MEM);
- hose->region_count = 1;
- pci_register_hose(hose);
-
- if (pcie_port_is_rootpoint(i))
- ppc4xx_setup_pcie_rootpoint(hose, i);
- else
- ppc4xx_setup_pcie_endpoint(hose, i);
-
- env = getenv("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
- if (delay > 5)
- printf("Warning, expect noticable delay before PCIe"
- "scan due to 'pciscandelay' value!\n");
- mdelay(delay * 1000);
- }
-
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
+ if (i > 0) {
+ puts(", serial# ");
+ puts(buf);
}
-}
-#endif
-
-#if defined(CONFIG_POST)
-/*
- * Returns 1 if keys pressed to start the power-on long-running tests
- * Called from board_init_f().
- */
-int post_hotkeys_pressed(void)
-{
- return 0; /* No hotkeys supported */
-}
-#endif /* CONFIG_POST */
+ printf(" (CPLD rev. %ld)\n", gd->board_type);
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
-void ft_board_setup(void *blob, bd_t *bd)
-{
- ft_cpu_setup(blob, bd);
+ return (0);
}
-#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
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