#include <ppc4xx.h>
#include <ppc405.h>
#include <libfdt.h>
+#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
*/
mtsdr(SDR0_SRST, 0);
- /*
- * Configure FPGA register with PCIe reset
- */
- out_be32((void *)CFG_FPGA_BASE, 0xff570cc0); /* assert PCIe reset */
- mdelay(50);
- out_be32((void *)CFG_FPGA_BASE, 0xff570cc3); /* deassert PCIe reset */
-
/* Configure 405EX for NAND usage */
val = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
(0x80000000 >> (28 + CFG_NAND_CS));
mtsdr(SDR0_CUST0, val);
+ /*
+ * Configure PFC (Pin Function Control) registers
+ * -> Enable USB
+ */
+ val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ;
+ mtsdr(SDR0_PFC1, val);
+
+ /*
+ * Configure FPGA register with PCIe reset
+ */
+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */
+ mdelay(50);
+ out_be32((void *)CFG_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */
+
return 0;
}
return 0;
}
-int board_emac_count(void)
+static int is_405exr(void)
{
u32 pvr = get_pvr();
+ if (pvr & 0x00000004)
+ return 0; /* bit 2 set -> 405EX */
+
+ return 1; /* bit 2 cleared -> 405EXr */
+}
+
+int board_emac_count(void)
+{
/*
* 405EXr only has one EMAC interface, 405EX has two
*/
- if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ if (is_405exr())
return 1;
else
return 2;
static int board_pcie_count(void)
{
- u32 pvr = get_pvr();
-
/*
* 405EXr only has one EMAC interface, 405EX has two
*/
- if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ if (is_405exr())
return 1;
else
return 2;
int checkboard (void)
{
char *s = getenv("serial#");
- u32 pvr = get_pvr();
- if ((pvr == PVR_405EXR1_RA) || (pvr == PVR_405EXR2_RA))
+ if (is_405exr())
printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board");
else
printf("Board: Kilauea - AMCC PPC405EX Evaluation Board");
pci_register_hose(hose);
if (is_end_point(i)) {
- ppc4xx_setup_pcie_endpoint(hose, i);
+ ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
- */
+ */
} else {
- ppc4xx_setup_pcie_rootpoint(hose, i);
+ ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
- if (env != NULL) {
- delay = simple_strtoul(env, NULL, 10);
+ if (env != NULL) {
+ delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
- printf("Warning, expect noticable delay before "
+ printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
- /*
- * Config access can only go down stream
- */
- hose->last_busno = pci_hose_scan(hose);
- bus = hose->last_busno + 1;
+ /*
+ * Config access can only go down stream
+ */
+ hose->last_busno = pci_hose_scan(hose);
+ bus = hose->last_busno + 1;
}
}
}