Merge branch 'master' into next

[u-boot] / board / amcc / sequoia / init.S

diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index bd346bf04b87698b9b408fa15b339a2c9b8ba961..3c0e400f9532526970b444f1f77c1137e748ac98 100644 (file)
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -43,12 +43,19 @@ tlbtab:
        /* vxWorks needs this as first entry for the Machine Check interrupt */
        tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 
+       /*
+        * The RAM-boot version skips the SDRAM TLB (identified by EPN=0). This
+        * entry is already configured for SDRAM via the JTAG debugger and mustn't
+        * be re-initialized by this RAM-booting U-Boot version.
+        */
+#ifndef CONFIG_SYS_RAMBOOT
        /* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
        tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
 #else
        tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 #endif
+#endif /* CONFIG_SYS_RAMBOOT */
 
        /* TLB-entry for EBC */
        tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
@@ -103,7 +110,7 @@ tlbtab:
 reconfig_tlb0:
        sync
        isync
-       addi    r4,r0,0x0000            /* TLB entry #0 */
+       addi    r4,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* TLB entry # */
        lis     r5,TLB00@h
        ori     r5,r5,TLB00@l
        tlbwe   r5,r4,0x0000            /* Save it out */