Merge with git://www.denx.de/git/u-boot.git

[u-boot] / board / amcc / sequoia / init.S

diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 45bcd4bef759ab385d745ff0120aaebca7b54abb..ff6ae669efb7bed64e0e5b55f51355ea1039d3f1 100644 (file)
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -20,57 +20,9 @@
  */
 
 #include <ppc_asm.tmpl>
+#include <asm-ppc/mmu.h>
 #include <config.h>
 
-/* General */
-#define TLB_VALID   0x00000200
-#define _256M       0x10000000
-
-/* Supported page sizes */
-
-#define SZ_1K      0x00000000
-#define SZ_4K      0x00000010
-#define SZ_16K     0x00000020
-#define SZ_64K     0x00000030
-#define SZ_256K            0x00000040
-#define SZ_1M      0x00000050
-#define SZ_8M       0x00000060
-#define SZ_16M     0x00000070
-#define SZ_256M            0x00000090
-
-/* Storage attributes */
-#define SA_W       0x00000800      /* Write-through */
-#define SA_I       0x00000400      /* Caching inhibited */
-#define SA_M       0x00000200      /* Memory coherence */
-#define SA_G       0x00000100      /* Guarded */
-#define SA_E       0x00000080      /* Endian */
-
-/* Access control */
-#define AC_X       0x00000024      /* Execute */
-#define AC_W       0x00000012      /* Write */
-#define AC_R       0x00000009      /* Read */
-
-/* Some handy macros */
-
-#define EPN(e)         ((e) & 0xfffffc00)
-#define TLB0(epn,sz)   ( (EPN((epn)) | (sz) | TLB_VALID ) )
-#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
-#define TLB2(a)                ( (a)&0x00000fbf )
-
-#define tlbtab_start\
-       mflr    r1  ;\
-       bl 0f       ;
-
-#define tlbtab_end\
-       .long 0, 0, 0   ;   \
-0:     mflr    r0      ;   \
-       mtlr    r1      ;   \
-       blr             ;
-
-#define tlbentry(epn,sz,rpn,erpn,attr)\
-       .long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
-
-
 /**************************************************************************
  * TLB TABLE
  *
@@ -98,7 +50,11 @@ tlbtab:
 #endif
 
        /* TLB-entry for DDR SDRAM (Up to 2GB) */
+#ifdef CONFIG_4xx_DCACHE
+       tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+#else
        tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+#endif
 
 #ifdef CFG_INIT_RAM_DCACHE
        /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
@@ -126,6 +82,9 @@ tlbtab:
        /* TLB-entry for peripherals */
        tlbentry( 0xEF000000, SZ_16M, 0xEF000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 
+       /* TLB-entry PCI IO Space - from sr@denx.de */
+       tlbentry(0xE8000000, SZ_64K, 0xE8000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
+
        tlbtab_end
 
 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)