Merge branch 'next' of git://git.denx.de/u-boot-mpc83xx

[u-boot] / board / amcc / sequoia / sdram.c

diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 53f728def9d576cae7a2af11f728608f7007eaa3..2c5a21806a31cd6072d45c464c425cde77a87f0e 100644 (file)
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -1,49 +1,62 @@
 /*
  * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
+ * Sylvie Gohl,             AMCC/IBM, gohl.sylvie@fr.ibm.com
+ * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
+ * Thierry Roman,           AMCC/IBM, thierry_roman@fr.ibm.com
+ * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
+ * Robert Snyder,           AMCC/IBM, rob.snyder@fr.ibm.com
  *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
+ * (C) Copyright 2006-2007
+ * Stefan Roese, DENX Software Engineering, sr@denx.de.
  *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
+/* define DEBUG for debug output */
+#undef DEBUG
+
 #include <common.h>
 #include <asm/processor.h>
-#include <ppc440.h>
+#include <asm/io.h>
+#include <asm/ppc440.h>
+
+/*-----------------------------------------------------------------------------+
+ * Prototypes
+ *-----------------------------------------------------------------------------*/
+extern int denali_wait_for_dlllock(void);
+extern void denali_core_search_data_eye(void);
+
+#if defined(CONFIG_NAND_SPL)
+/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+ * for the 4k NAND boot image so define bus_frequency to 133MHz here
+ * which is save for the refresh counter setup.
+ */
+#define get_bus_freq(val)      133333333
+#endif
 
 /*************************************************************************
  *
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-       volatile ulong val;
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
+    defined(CONFIG_NAND_SPL)
+       ulong speed = get_bus_freq(0);
 
        mtsdram(DDR0_02, 0x00000000);
 
        mtsdram(DDR0_00, 0x0000190A);
        mtsdram(DDR0_01, 0x01000000);
        mtsdram(DDR0_03, 0x02030602);
-       mtsdram(DDR0_04, 0x13030300);
-       mtsdram(DDR0_05, 0x0202050E);
-       mtsdram(DDR0_06, 0x0104C823);
+       mtsdram(DDR0_04, 0x0A020200);
+       mtsdram(DDR0_05, 0x02020308);
+       mtsdram(DDR0_06, 0x0102C812);
        mtsdram(DDR0_07, 0x000D0100);
-       mtsdram(DDR0_08, 0x02360001);
+       mtsdram(DDR0_08, 0x02430001);
        mtsdram(DDR0_09, 0x00011D5F);
-       mtsdram(DDR0_10, 0x00000300);
+       mtsdram(DDR0_10, 0x00000100);
        mtsdram(DDR0_11, 0x0027C800);
        mtsdram(DDR0_12, 0x00000003);
        mtsdram(DDR0_14, 0x00000000);
@@ -55,23 +68,34 @@ long int initdram (int board_type)
        mtsdram(DDR0_22, 0x00267F0B);
        mtsdram(DDR0_23, 0x00000000);
        mtsdram(DDR0_24, 0x01010002);
-       mtsdram(DDR0_26, 0x5B260181);
+       if (speed > 133333334)
+               mtsdram(DDR0_26, 0x5B26050C);
+       else
+               mtsdram(DDR0_26, 0x5B260408);
        mtsdram(DDR0_27, 0x0000682B);
        mtsdram(DDR0_28, 0x00000000);
        mtsdram(DDR0_31, 0x00000000);
        mtsdram(DDR0_42, 0x01000006);
-       mtsdram(DDR0_43, 0x050A0200);
-       mtsdram(DDR0_44, 0x00000005);
+       mtsdram(DDR0_43, 0x030A0200);
+       mtsdram(DDR0_44, 0x00000003);
        mtsdram(DDR0_02, 0x00000001);
 
+       denali_wait_for_dlllock();
+#endif /* #ifndef CONFIG_NAND_U_BOOT */
+
+#ifdef CONFIG_DDR_DATA_EYE
+       /* -----------------------------------------------------------+
+        * Perform data eye search if requested.
+        * ----------------------------------------------------------*/
+       denali_core_search_data_eye();
+#endif
+
        /*
-        * Wait for DCC master delay line to finish calibration
+        * Clear possible errors resulting from data-eye-search.
+        * If not done, then we could get an interrupt later on when
+        * exceptions are enabled.
         */
-       mfsdram(DDR0_17, val);
-       while (((val >> 8) & 0x000007f) == 0) {
-               mfsdram(DDR0_17, val);
-       }
-#endif /* #ifndef CONFIG_NAND_U_BOOT */
+       set_mcsr(get_mcsr());
 
-       return (CFG_MBYTES_SDRAM << 20);
+       return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }