board/esd/cpci5200/strataflash.c: Fix GCC 4.6 build warning

[u-boot] / board / amcc / sequoia / sdram.c

diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 5e93f6c7a090e3880bf980112043a234c03589bd..5c01deff9fd5b19d9c8b95748b43a1060161baad 100644 (file)
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -31,7 +31,7 @@
 #include <common.h>
 #include <asm/processor.h>
 #include <asm/io.h>
-#include <ppc440.h>
+#include <asm/ppc440.h>
 
 /*-----------------------------------------------------------------------------+
  * Prototypes
@@ -40,11 +40,11 @@ extern int denali_wait_for_dlllock(void);
 extern void denali_core_search_data_eye(void);
 
 #if defined(CONFIG_NAND_SPL)
-/* Using cpu/ppc4xx/speed.c to calculate the bus frequency is too big
+/* Using arch/powerpc/cpu/ppc4xx/speed.c to calculate the bus frequency is too big
  * for the 4k NAND boot image so define bus_frequency to 133MHz here
  * which is save for the refresh counter setup.
  */
-#define get_bus_freq(val)      133000000
+#define get_bus_freq(val)      133333333
 #endif
 
 /*************************************************************************
@@ -52,14 +52,11 @@ extern void denali_core_search_data_eye(void);
  * initdram -- 440EPx's DDR controller is a DENALI Core
  *
  ************************************************************************/
-long int initdram (int board_type)
+phys_size_t initdram (int board_type)
 {
-#if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-#if !defined(CONFIG_NAND_SPL)
+#if !(defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_SYS_RAMBOOT)) || \
+    defined(CONFIG_NAND_SPL)
        ulong speed = get_bus_freq(0);
-#else
-       ulong speed = 133333333;        /* 133MHz is on the safe side   */
-#endif
 
        mtsdram(DDR0_02, 0x00000000);
 
@@ -72,7 +69,7 @@ long int initdram (int board_type)
        mtsdram(DDR0_07, 0x000D0100);
        mtsdram(DDR0_08, 0x02430001);
        mtsdram(DDR0_09, 0x00011D5F);
-       mtsdram(DDR0_10, 0x00000300);
+       mtsdram(DDR0_10, 0x00000100);
        mtsdram(DDR0_11, 0x0027C800);
        mtsdram(DDR0_12, 0x00000003);
        mtsdram(DDR0_14, 0x00000000);
@@ -106,5 +103,12 @@ long int initdram (int board_type)
        denali_core_search_data_eye();
 #endif
 
-       return (CFG_MBYTES_SDRAM << 20);
+       /*
+        * Clear possible errors resulting from data-eye-search.
+        * If not done, then we could get an interrupt later on when
+        * exceptions are enabled.
+        */
+       set_mcsr(get_mcsr());
+
+       return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }