* MA 02111-1307 USA
*/
#include <common.h>
+#include <netdev.h>
#include <asm/arch/omap2420.h>
#include <asm/io.h>
#include <asm/arch/bits.h>
********************************************************/
int misc_init_r(void)
{
- ether_init(); /* better done here so timers are init'ed */
return (0);
}
}
/*******************************************************************
- * Routine:ether_init
+ * Routine:board_eth_init
* Description: take the Ethernet controller out of reset and wait
- * for the EEPROM load to complete.
+ * for the EEPROM load to complete.
******************************************************************/
-void ether_init(void)
+int board_eth_init(bd_t *bis)
{
-#ifdef CONFIG_DRIVER_LAN91C96
+ int rc = 0;
+#ifdef CONFIG_LAN91C96
int cnt = 20;
__raw_writeb(0x03, OMAP2420_CTRL_BASE + 0x0f2); /*protect->gpio74 */
do {
__raw_writew(0x1, LAN_RESET_REGISTER);
udelay(100);
- if (cnt == 0) {
- printf("1. eth reset err\n");
+ if (cnt == 0)
goto eth_reset_err_out;
- }
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x1);
do {
__raw_writew(0x0, LAN_RESET_REGISTER);
udelay(100);
- if (cnt == 0) {
- printf("2. eth reset err\n");
+ if (cnt == 0)
goto eth_reset_err_out;
- }
--cnt;
} while (__raw_readw(LAN_RESET_REGISTER) != 0x0000);
udelay(1000);
mask_config_reg(ETH_CONTROL_REG, 0x01);
udelay(1000);
-
+ rc = lan91c96_initialize(0, CONFIG_LAN91C96_BASE);
eth_reset_err_out:
- return;
#endif
+ return rc;
}
/**********************************************
__raw_writel(v, CM_CLKSEL2_CORE);
__raw_writel(0x1, CM_CLKSEL_WKUP);
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
/* Enable UART1 clock */
func_clks |= BIT21;
if_clks |= BIT21;
void muxSetupGPMC(void)
{
/* gpmc_io_dir, MCR */
- writel(0x4800008C, 0x19000000);
+ volatile unsigned int *MCR = (unsigned int *) 0x4800008C;
+ *MCR = 0x19000000;
/* NOR FLASH CS0 */
/* signal - Gpmc_clk; pin - J4; offset - 0x0088; mode 0; Byte-3 */