riscv: ae250: Support DT provided by the board at runtime

[u-boot] / board / astro / mcf5373l / fpga.c

diff --git a/board/astro/mcf5373l/fpga.c b/board/astro/mcf5373l/fpga.c
index c679ad7f65c6f9664549e98aa90f0b3198c49014..53e00728c3d8894904847094c5bfc369bab22abf 100644 (file)
--- a/board/astro/mcf5373l/fpga.c
+++ b/board/astro/mcf5373l/fpga.c
@@ -15,6 +15,7 @@
 /* Altera/Xilinx FPGA configuration support for the ASTRO "URMEL" board */
 
 #include <common.h>
+#include <console.h>
 #include <watchdog.h>
 #include <altera.h>
 #include <ACEX1K.h>
@@ -100,7 +101,7 @@ int altera_done_fn(int cookie)
  * writing the complete buffer in one function is much faster,
  * then calling it for every bit
  */
-int altera_write_fn(void *buf, size_t len, int flush, int cookie)
+int altera_write_fn(const void *buf, size_t len, int flush, int cookie)
 {
        size_t bytecount = 0;
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -203,7 +204,7 @@ int astro5373l_altera_load(void)
 }
 
 /* Set the FPGA's PROG_B line to the specified level */
-int xilinx_pgm_fn(int assert, int flush, int cookie)
+int xilinx_pgm_config_fn(int assert, int flush, int cookie)
 {
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
 
@@ -218,7 +219,7 @@ int xilinx_pgm_fn(int assert, int flush, int cookie)
  * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
  * asserted (low).
  */
-int xilinx_init_fn(int cookie)
+int xilinx_init_config_fn(int cookie)
 {
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
 
@@ -226,7 +227,7 @@ int xilinx_init_fn(int cookie)
 }
 
 /* Test the state of the active-high FPGA DONE pin */
-int xilinx_done_fn(int cookie)
+int xilinx_done_config_fn(int cookie)
 {
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
 
@@ -234,7 +235,7 @@ int xilinx_done_fn(int cookie)
 }
 
 /* Abort an FPGA operation */
-int xilinx_abort_fn(int cookie)
+int xilinx_abort_config_fn(int cookie)
 {
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
        /* ensure all SPI peripherals and FPGAs are deselected */
@@ -300,7 +301,7 @@ int xilinx_post_config_fn(int cookie)
        return rc;
 }
 
-int xilinx_clk_fn(int assert_clk, int flush, int cookie)
+int xilinx_clk_config_fn(int assert_clk, int flush, int cookie)
 {
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
 
@@ -311,7 +312,7 @@ int xilinx_clk_fn(int assert_clk, int flush, int cookie)
        return assert_clk;
 }
 
-int xilinx_wr_fn(int assert_write, int flush, int cookie)
+int xilinx_wr_config_fn(int assert_write, int flush, int cookie)
 {
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
 
@@ -322,7 +323,7 @@ int xilinx_wr_fn(int assert_write, int flush, int cookie)
        return assert_write;
 }
 
-int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
+int xilinx_fastwr_config_fn(void *buf, size_t len, int flush, int cookie)
 {
        size_t bytecount = 0;
        gpio_t *gpiop = (gpio_t *)MMAP_GPIO;
@@ -363,23 +364,24 @@ int xilinx_fastwr_fn(void *buf, size_t len, int flush, int cookie)
  * relocated at runtime.
  * FIXME: relocation not yet working for coldfire, see below!
  */
-Xilinx_Spartan3_Slave_Serial_fns xilinx_fns = {
+xilinx_spartan3_slave_serial_fns xilinx_fns = {
        xilinx_pre_config_fn,
-       xilinx_pgm_fn,
-       xilinx_clk_fn,
-       xilinx_init_fn,
-       xilinx_done_fn,
-       xilinx_wr_fn,
+       xilinx_pgm_config_fn,
+       xilinx_clk_config_fn,
+       xilinx_init_config_fn,
+       xilinx_done_config_fn,
+       xilinx_wr_config_fn,
        0,
-       xilinx_fastwr_fn
+       xilinx_fastwr_config_fn
 };
 
-Xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
-       {Xilinx_Spartan3,
+xilinx_desc xilinx_fpga[CONFIG_FPGA_COUNT] = {
+       {xilinx_spartan3,
         slave_serial,
         XILINX_XC3S4000_SIZE,
         (void *)&xilinx_fns,
-        0}
+        0,
+        &spartan3_op}
 };
 
 /* Initialize the fpga.  Return 1 on success, 0 on failure. */
@@ -395,12 +397,12 @@ int astro5373l_xilinx_load(void)
                 * so set stuff here instead of static initialisation:
                 */
                xilinx_fns.pre = xilinx_pre_config_fn;
-               xilinx_fns.pgm = xilinx_pgm_fn;
-               xilinx_fns.clk = xilinx_clk_fn;
-               xilinx_fns.init = xilinx_init_fn;
-               xilinx_fns.done = xilinx_done_fn;
-               xilinx_fns.wr = xilinx_wr_fn;
-               xilinx_fns.bwr = xilinx_fastwr_fn;
+               xilinx_fns.pgm = xilinx_pgm_config_fn;
+               xilinx_fns.clk = xilinx_clk_config_fn;
+               xilinx_fns.init = xilinx_init_config_fn;
+               xilinx_fns.done = xilinx_done_config_fn;
+               xilinx_fns.wr = xilinx_wr_config_fn;
+               xilinx_fns.bwr = xilinx_fastwr_config_fn;
                xilinx_fpga[i].iface_fns = (void *)&xilinx_fns;
                fpga_add(fpga_xilinx, &xilinx_fpga[i]);
        }