#include <asm/io.h>
#include <asm/sdram.h>
#include <asm/arch/clk.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/hmatrix2.h>
+#include <asm/arch/hmatrix.h>
+#include <asm/arch/mmu.h>
+#include <asm/arch/portmux.h>
+#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
-#ifdef CONFIG_ATSTK1006
-/* Dual MT48LC16M16A2-7E on daughterboard */
-static const struct sdram_info sdram = {
- .phys_addr = CFG_SDRAM_BASE,
+struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
+ {
+ .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT,
+ .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_NONE,
+ }, {
+ .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT,
+ .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT,
+ .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT)
+ | MMU_VMR_CACHE_WRBACK,
+ },
+};
+
+static const struct sdram_config sdram_config = {
+#if defined(CONFIG_ATSTK1006)
+ /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
+ .data_bits = SDRAM_DATA_32BIT,
.row_bits = 13,
.col_bits = 9,
.bank_bits = 2,
.txsr = 7,
/* 7.81 us */
.refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
-};
#else
-/* MT48LC2M32B2-5 on motherboard */
-static const struct sdram_info sdram = {
- .phys_addr = CFG_SDRAM_BASE,
+ /* MT48LC2M32B2P-5 (8 MB) on motherboard */
+#ifdef CONFIG_ATSTK1004
+ .data_bits = SDRAM_DATA_16BIT,
+#else
+ .data_bits = SDRAM_DATA_32BIT,
+#endif
+#ifdef CONFIG_ATSTK1000_16MB_SDRAM
+ /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
+ .row_bits = 12,
+#else
.row_bits = 11,
+#endif
.col_bits = 8,
.bank_bits = 2,
.cas = 3,
.txsr = 5,
/* 15.6 us */
.refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
-};
#endif
+};
int board_early_init_f(void)
{
- /* Set the SDRAM_ENABLE bit in the HEBI SFR */
- hmatrix2_writel(SFR4, 1 << 1);
+ /* Enable SDRAM in the EBI mux */
+ hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
- gpio_enable_ebi();
- gpio_enable_usart1();
+ portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
+ portmux_enable_usart1(PORTMUX_DRIVE_MIN);
#if defined(CONFIG_MACB)
- gpio_enable_macb0();
- gpio_enable_macb1();
+ portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
+ portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
#endif
#if defined(CONFIG_MMC)
- gpio_enable_mmci();
+ portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
#endif
return 0;
}
-long int initdram(int board_type)
+phys_size_t initdram(int board_type)
{
- return sdram_init(&sdram);
+ unsigned long expected_size;
+ unsigned long actual_size;
+ void *sdram_base;
+
+ sdram_base = uncached(EBI_SDRAM_BASE);
+
+ expected_size = sdram_init(sdram_base, &sdram_config);
+ actual_size = get_ram_size(sdram_base, expected_size);
+
+ if (expected_size != actual_size)
+ printf("Warning: Only %lu of %lu MiB SDRAM is working\n",
+ actual_size >> 20, expected_size >> 20);
+
+ return actual_size;
}
-void board_init_info(void)
+int board_early_init_r(void)
{
gd->bd->bi_phy_id[0] = 0x10;
gd->bd->bi_phy_id[1] = 0x11;
+ return 0;
}
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bi)
+{
+ macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
+ macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
+ return 0;
+}
+#endif