travis-ci: Drop 'TEST_CMD'

[u-boot] / board / atmel / sama5d4ek / sama5d4ek.c

diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c
index f8394f577e2c22aee2e1e56c23c4ba8f6b55a31c..72bad230871d1994f489bf92f79750ffdb9afa39 100644 (file)
--- a/board/atmel/sama5d4ek/sama5d4ek.c
+++ b/board/atmel/sama5d4ek/sama5d4ek.c
@@ -8,13 +8,14 @@
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/at91_common.h>
-#include <asm/arch/at91_pmc.h>
 #include <asm/arch/at91_rstc.h>
+#include <asm/arch/atmel_mpddrc.h>
+#include <asm/arch/atmel_usba_udc.h>
 #include <asm/arch/gpio.h>
 #include <asm/arch/clk.h>
 #include <asm/arch/sama5d3_smc.h>
 #include <asm/arch/sama5d4.h>
-#include <atmel_lcdc.h>
+#include <atmel_hlcdc.h>
 #include <atmel_mci.h>
 #include <lcd.h>
 #include <mmc.h>
@@ -22,6 +23,7 @@
 #include <netdev.h>
 #include <nand.h>
 #include <spi.h>
+#include <version.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -111,7 +113,6 @@ vidinfo_t panel_info = {
        .vl_col = 800,
        .vl_row = 480,
        .vl_clk = 33260000,
-       .vl_sync = ATMEL_LCDC_INVLINE_NORMAL | ATMEL_LCDC_INVFRAME_NORMAL,
        .vl_bpix = LCD_BPP,
        .vl_tft = 1,
        .vl_hsync_len = 5,
@@ -173,6 +174,7 @@ void lcd_show_board_info(void)
        int i;
        char temp[32];
 
+       lcd_printf("%s\n", U_BOOT_VERSION);
        lcd_printf("2014 ATMEL Corp\n");
        lcd_printf("at91@atmel.com\n");
        lcd_printf("%s CPU at %s MHz\n", get_cpu_name(),
@@ -185,7 +187,7 @@ void lcd_show_board_info(void)
        nand_size = 0;
 #ifdef CONFIG_NAND_ATMEL
        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
-               nand_size += nand_info[i].size;
+               nand_size += nand_info[i]->size;
 #endif
        lcd_printf("%ld MB SDRAM, %ld MB NAND\n",
                   dram_size >> 20, nand_size >> 20);
@@ -294,6 +296,9 @@ int board_init(void)
 #ifdef CONFIG_CMD_USB
        sama5d4ek_usb_hw_init();
 #endif
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       at91_udp_hw_init();
+#endif
 
        return 0;
 }
@@ -313,5 +318,94 @@ int board_eth_init(bd_t *bis)
        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_GMAC0, 0x00);
 #endif
 
+#ifdef CONFIG_USB_GADGET_ATMEL_USBA
+       usba_udc_probe(&pdata);
+#ifdef CONFIG_USB_ETH_RNDIS
+       usb_eth_initialize(bis);
+#endif
+#endif
+
        return rc;
 }
+
+/* SPL */
+#ifdef CONFIG_SPL_BUILD
+void spl_board_init(void)
+{
+#ifdef CONFIG_SYS_USE_MMC
+       sama5d4ek_mci1_hw_init();
+#elif CONFIG_SYS_USE_NANDFLASH
+       sama5d4ek_nand_hw_init();
+#elif CONFIG_SYS_USE_SERIALFLASH
+       sama5d4ek_spi0_hw_init();
+#endif
+}
+
+static void ddr2_conf(struct atmel_mpddrc_config *ddr2)
+{
+       ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM);
+
+       ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 |
+                   ATMEL_MPDDRC_CR_NR_ROW_14 |
+                   ATMEL_MPDDRC_CR_CAS_DDR_CAS3 |
+                   ATMEL_MPDDRC_CR_NB_8BANKS |
+                   ATMEL_MPDDRC_CR_NDQS_DISABLED |
+                   ATMEL_MPDDRC_CR_DECOD_INTERLEAVED |
+                   ATMEL_MPDDRC_CR_UNAL_SUPPORTED);
+
+       ddr2->rtr = 0x2b0;
+
+       ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET |
+                     10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET);
+
+       ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET |
+                     200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET |
+                     25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET |
+                     23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET);
+
+       ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET |
+                     3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET |
+                     2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET |
+                     8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET);
+}
+
+void mem_init(void)
+{
+       struct atmel_mpddrc_config ddr2;
+
+       ddr2_conf(&ddr2);
+
+       /* Enable MPDDR clock */
+       at91_periph_clk_enable(ATMEL_ID_MPDDRC);
+       at91_system_clk_enable(AT91_PMC_DDR);
+
+       /* DDRAM2 Controller initialize */
+       ddr2_init(ATMEL_BASE_MPDDRC, ATMEL_BASE_DDRCS, &ddr2);
+}
+
+void at91_pmc_init(void)
+{
+       u32 tmp;
+
+       tmp = AT91_PMC_PLLAR_29 |
+             AT91_PMC_PLLXR_PLLCOUNT(0x3f) |
+             AT91_PMC_PLLXR_MUL(87) |
+             AT91_PMC_PLLXR_DIV(1);
+       at91_plla_init(tmp);
+
+       at91_pllicpr_init(AT91_PMC_IPLL_PLLA(0x0));
+
+       tmp = AT91_PMC_MCKR_H32MXDIV |
+             AT91_PMC_MCKR_PLLADIV_2 |
+             AT91_PMC_MCKR_MDIV_3 |
+             AT91_PMC_MCKR_CSS_PLLA;
+       at91_mck_init(tmp);
+}
+#endif